문서를 보다 보니 Active Serial / Passive Serial 이라는 단어가 나와서 검색해보니..
일단 Active/Passive는 FPGA의 기준으로 보면 될 것 같다.
Active Serial은 FPGA가 활성화 되서 master 로서 EPCS나 EPCQ를 쓰는 것이고
Passive Serial은 FPGA가 플래시에 관여하지 않고 별도의 micom이나 다른 장치를 통해 플래시를 굽는 것이다.
[링크 : https://www.altera.com/support/support-resources/support-centers/devices/cfg-index/cfg-compare.html]
The Active Serial (AS) configuration scheme is supported in the 1 bit data width (AS x1) or the 4 bit data width (AS x4). The AS x4 scheme is supported only in Stratix® V devices. AS configuration can be performed using an Altera® serial configuration (EPCS) device or quad-serial configuration (EPCQ) device. During AS configuration, the Altera FPGA acts as the configuration master and the EPCS or EPCQ device acts as the configuration slave. The FPGA outputs the clock on the DCLK pin and receives the configuration data from the EPCS or EPCQ device on the data pin(s).
[링크 : https://www.altera.com/support/support-resources/support-centers/devices/cfg-index/cfg-as.html]
Passive serial (PS) configuration can be performed using an Altera® download cable, an Altera configuration device, or an intelligent host such as a microprocessor. During PS configuration, data is transferred from a configuration device, flash memory, or other storage device to the Altera device on the DATA0 pin. This configuration data is latched into the FPGA on the rising edge of DCLK. Configuration data is transferred at a rate of one bit per clock cycle.
[링크 : https://www.altera.com/support/support-resources/support-centers/devices/cfg-index/cfg-ps.html]
[링크 : https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_usb_blstr.pdf]
To program a device in JTAG or Passive Serial mode:
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[링크 : http://quartushelp.altera.com/15.0/mergedProjects/program/pgm/pgm_pro_prog_single_as_device.htm]
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