구차니의 잡동사니 모음

3.1일부터 희망도서 신청 규정이 변경됨을 알려드립니다.

oo시도서관 희망도서신청 규정 알림

• 희망도서 구입제외도서
  • 1. 우리도서관이 소장하고 있거나 정기구입 자료에 포함된 자료
  • 2. 비도서자료, 연속간행물(일간지, 주간지등) 및 수험서, 문제집
  • 3. 5권 이상의 전집류, 전공서적, 1권당 3만원 이상의 고가서적, 원서
     * 단, 3만원 이상의 고가서적은 선별하여 신간도서로 구입하겠습니다.
  • 4. 만화/판타지/무협지/로맨스 소설 등
  • 5. 등급이 18세 이상의 성인자료
  • 6. 통상적인 형태가 아닌 자료(너무 크거나 작은 자료, 스프링 제본 도서 등)
  • 7. 출간된 지 5년 이상 된 자료(컴퓨터/과학 등의 자료는 2년 이내)
  • 8. 기타 도서관에 소장이 부적합하다고 판단되는 자료 등
• 주의사항
  • 1. 월별 회원 당 oo시도서관 전체에서 최대 5권까지
     → 가족대표자에 한함
  • 2. 입수된 희망도서는 희망자에게 개별 통보 후 3일 이내 우선 대출됨
     → 신청한 희망도서를 3일내 대출하지 않은 이력이 2회 이상인 경우 3개월간 신청 제한
  • 3. 3일이 지난 후 희망자가 대출하지 않을 경우 각 자료실 서가에 비치 

library ieee;

use ieee.std_logic_1164.all; entity AndOr_vhdl is port( a,b : in std_logic; and_out, or_out, not_out : out std_logic); end AndOr_whdl; architecture design of AndOr_vhdl is begin and_out <= a and b; or_out <= a or b; not_out <= not a; end design;

LUT, Logic Cell and Logic Element are all the same to me: the most basic FPGA general logic primitive. Xilinx use LUT, Altera LE, microsemi/lattice possibly something else.

The problem is, they are not the same. In their most recent architecture, Xilinx use 6-input LUT and altera 4-input LUT. They are aggregated in logic blocks which has other features like fast-carry chain, registers and distributed memory.

Converting to system gates is useful, but don't forget it's also a marketing war. A Xilinx FPGA should fit 1.5 times the logic of an Altera FPGA, since it's LUT have 6 instead of 4, right? Well, it largely depends on the design, if the design can't use 6-inputs much, the unused ones are wasted. Same with fast-carry logic, I don't know if they count that in equivalent gate number, but be advised that number is inflated.

System gates is a common measure of ASIC design complexity. The same design on two different foundries should have similar system gates number, as waste is not really an issue for ASIC.

If you're looking for an FPGA. I suggest you choose your vendor, port enough of your design to get an idea of how big a FPGA you need and choose a FPGA with an upgrade path (if you want to market). If it's for a single prototype, just use the biggest FPGA you can afford. 

Logic array blocks (LABs) contain groups of LEs. 

Each LAB consists of the following features: 

■ 16 LEs

High-performance FPGA fabric Enhanced 8-input ALM with four registers 

The PCIe endpoint support includes multifunction support for up to eight functions, as shown in the following figure. The integrated multifunction support reduces the FPGA logic requirements by up to 20,000 LEs for PCIe designs that require multiple peripherals. 

Designing the ALM The ALM is radically different from any other FPGA logic block, offering a number of major innovations. Getting from a classic 4-LUT with a single register block (with associated carry logic) to the ALM required a detailed understanding of customer requirements and a large investment in researching the tradeoffs of various architectures. Our pursuit for a larger LUT was inspired by research results indicating that a basic 6-LUT could yield a 14% performance improvement by reducing the number of levels of logic elements on the critical paths of circuits. Unfortunately, this performance increase also had a large area penalty, a 17% area increase resulting from a larger LUT-mask and more inputs for the LUT. Figure 4 illustrates the tradeoff between cost and delay for different sizes of LUTs. The basic approach in designing the ALM was to investigate building a larger LUT to reduce levels of logic and increase performance, but to also avoid the area increase by efficiently dividing the larger LUT into smaller LUTs when appropriate, as illustrated by the dashed line. The ability to divide a LUT is what makes it “adaptive.”