EPCS Controller 추가 및 jic 통합하기.. 실패중

그래도 안되네 ㅠㅠ

설정 가능한 내용으로는 딱히 눈에 띄는건 없네

심심해서 SDRAM은 어떻게 추가하나했는데.. university program에 DE 보드 관련 SDRAM PLL은 존재하고

SDRAM은 별도로 추가를 해주어야 한다. (ISSI 칩 기본 프리셋 존재하지 않음)

이제 남은건.. sof 파일을 hex로 바꾸는건가...

sof를 시작주소 줄 수 있었군..

최소한 이렇게 하면, Nios II 자체는 구동하는걸로 보인다(LED 불 전부 꺼짐)

eclipse에서 테스트 해보니 장치 인식을 하는 것 봐서 정상적으로 Nios II는 들어간 듯

[링크 : https://www.alteraforum.com/forum/showthread.php?t=48733]

10. Click SOF Data, and select Add File, and select your .sof file 11. Click Add Hex data, select Relative addressing, and select your .hex file created above 12. Now push generate. You should verify that the generated .map file has Page_0 at a start address of 0x0, and the hex file at a start address 1 after the end address of Page_0 13. Now in the Quartus II Programmer, select Add File and select your .jic file. Check the Program box next to the .jic file, and push Start

[링크 : https://www.altera.com/support/support-resources/knowledge-base/solutions/rd10132010_126.html]

Creating the .jic file: In Quartus, open the Convert "Programming File..." utility Set the "Programming file type:" to "JTAG Indirect Configuration File (.jic)" In "Input files to convert" select "Flash Loader", click "Add Device..." and choose your target FPGA device If you are configuring the FPGA from the serial flash: In "Input files to convert" select "SOF Data", click "Add File..." and select your FPGA .sof file -With "SOF Data" selected, click "Properties", in the "SOF Data Properies dialogue box: -Set "Address mode for selected pages to" to "Start" Set "Start address (32-bit hexidecimal:) to 0x0. In "Input files to convert" click "Add Hex Data", in the "Add Hex Data" dialogue box: Set "Addressing mode" to "Absolute addressing" Select your hex file using the "..." button next to the "Hex file" field Click "OK" Check "Create Memory Map File". This is useful for debugging. Generate the .jic file and program it into the serial flash with the Quartus Programmer

[링크 : http://www.alterawiki.com/wiki/Booting_Nios_from_Serial_Flash_with_the_new_Altera_Serial_Flash_Controller]

그나저나 빌드 메시지를 보니..

13:50:21 **** Build of configuration Nios II for project hello_world_0 **** make mem_init_generate  Info: Building ../hello_world_0_bsp/ C:/intelFPGA_lite/17.1/nios2eds/bin/gnu/H-x86_64-mingw32/bin/make --no-print-directory -C ../hello_world_0_bsp/ [BSP build complete] Post-processing to create mem_init/hdl_sim/unsaved_epcs_flash_controller_0_boot_rom.hex... elf2hex hello_world_0.elf 0x00011000 0x000117ff --width=32 --little-endian-mem --create-lanes=0 --no-zero-fill mem_init/hdl_sim/unsaved_epcs_flash_controller_0_boot_rom.hex Post-processing to create mem_init/unsaved_onchip_memory2_0.hex... elf2hex hello_world_0.elf 0x00008000 0x0000ffff --width=32 --little-endian-mem --create-lanes=0 mem_init/unsaved_onchip_memory2_0.hex Post-processing to create mem_init/hdl_sim/unsaved_epcs_flash_controller_0_boot_rom.dat... elf2dat --infile=hello_world_0.elf --outfile=mem_init/hdl_sim/unsaved_epcs_flash_controller_0_boot_rom.dat \ --base=0x00011000 --end=0x000117ff --width=32 \ --little-endian-mem --create-lanes=0  Post-processing to create mem_init/hdl_sim/unsaved_onchip_memory2_0.dat... elf2dat --infile=hello_world_0.elf --outfile=mem_init/hdl_sim/unsaved_onchip_memory2_0.dat \ --base=0x00008000 --end=0x0000ffff --width=32 \ --little-endian-mem --create-lanes=0  Post-processing to create mem_init/hdl_sim/unsaved_epcs_flash_controller_0_boot_rom.sym... nios2-elf-nm -n hello_world_0.elf > mem_init/hdl_sim/unsaved_epcs_flash_controller_0_boot_rom.sym Post-processing to create mem_init/hdl_sim/unsaved_onchip_memory2_0.sym... nios2-elf-nm -n hello_world_0.elf > mem_init/hdl_sim/unsaved_onchip_memory2_0.sym Post-processing to create unsaved_epcs_flash_controller_0_boot_rom.flash... elf2flash --input=hello_world_0.elf --outfile=unsaved_epcs_flash_controller_0_boot_rom.flash --sim_optimize=0 --little-endian-mem \  --epcs  Post-processing to create mem_init/meminit.spd... Post-processing to create mem_init/meminit.qip... 13:50:26 Build Finished (took 4s.961ms)

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귀찮아서(!) 안하려고 했던 sof2flash를 꼭 거쳐야 하나보다.. 나처럼 EPCS에 구우려면..

3.3.1.3 EPCS Parameters 3.3.2 Programming Both Hardware and Software into an EPCS/EPCQ Device The --base parameter is not available for EPCS/EPCQ devices, because in EPCS/EPCQ devices, FPGA configuration data must start at address 0x0. However, if you are programming both an FPGA configuration and a Nios II software executable in the EPCS/EPCQ device, the --after parameter lets you position the software executable directly after the FPGA configuration data. Convert the FPGA configuration file first using sof2flash. When converting the Nios II software executable, use the --after parameter, and specify the FPGA configuration S-record file. The S-record output for the software executable starts at the first address unused by the FPGA configuration. Refer to the second example under the “elf2flash Command-Line Examples” chapter. Note: elf2flash does not insert the FPGA configuration into the output file. It simply leaves space, starting at offset 0x0, that is large enough for the configuration data. Note: In Intel Quartus Prime software version 13.1 and onwards, the -epcs/--epcq option in sof2flash generates .flash file with a SOF header, which contains the SOF length. This change is required for V-series devices and above for new SOF format, and to allow for future SOF format variations. The Nios II bootcopier loads the Nios II software executable from EPCS/EPCQ devices based on the SOF length. For more information about how to program EPCS/EPCQ devices, refer to the "KDB Solution rd11192013_118" webpage. Related Links • elf2flash Command-Line Examples on page 25 • KDB Solution rd11192013_118

[링크 : https://www.altera.com/en_US/pdfs/literature/ug/ug_nios2_flash_programmer.pdf]

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카페 자료 뒤지다 보니,

Eclipse에 Flash Programmer가 있대서 보니 오.. 이런게 있네..

그런데 프로젝트도 안 부르고 그냥 실했더니 먼가 에러뿜뿜

아무튼 이걸 이용하면 굳이 jic 안만들어도 EPCS controller가 있으면 EPCS에 쓸 수 있다고 한다. 

[링크 : https://www.altera.com/en_US/pdfs/literature/ug/ug_nios2_flash_programmer.pdf]