xilinx bitstram ecryption

artix는 지원하나 모르겠네..

Virtex-6 and 7-Series devices support the use of both HMAC and AES keys. 

Spartan devices only have the AES key option. 

[링크 : https://www.xilinx.com/support/answers/52881.html]

[링크 : https://www.xilinx.com/support/documentation/application_notes/xapp1239-fpga-bitstream-encryption.pdf]

7 시리즈는 모두 지원을 하는 것으로 근래 변경된 듯?

The original plan was the smaller Artix would not have the AES/HMAC and XADC blocks. This was changed pretty recently - now all 7 series devices will be uniform in the support of these features.

[링크 : https://forums.xilinx.com/t5/7-Series-FPGAs/AES-encryption-in-Artix-7/td-p/156150]

표에 의하면 Spartan-7중 XC7S6 XC7S15는 제외 나머지 전 모델은 AES/HMAC을 지원하는 것으로 보인다.

[링크 : https://www.xilinx.com/support/documentation/selection-guides/7-series-product-selection-guide.pdf]

Encryption, Readback, and Partial Reconfiguration In all 7 series FPGAs (except XC7S6 and XC7S15), the FPGA bitstream, which contains sensitive customer IP, can be protected with 256-bit AES encryption and HMAC/SHA-256 authentication to prevent unauthorized copying of the design. The FPGA performs decryption on the fly during configuration using an internally stored 256-bit key. This key can reside in battery-backed RAM or in nonvolatile eFUSE bits. Most configuration data can be read back without affecting the system's operation. Typically, configuration is an all-or-nothing operation, but Xilinx 7 series FPGAs support partial reconfiguration. This is an extremely powerful and flexible feature that allows the user to change portions of the FPGA while other portions remain static. Users can time-slice these portions to fit more IP into smaller devices, saving cost and power. Where applicable in certain designs, partial reconfiguration can greatly improve the versatility of the FPGA.

[링크 : https://www.xilinx.com/support/documentation/data_sheets/ds180_7Series_Overview.pdf]