구차니의 잡동사니 모음

LUT, Logic Cell and Logic Element are all the same to me: the most basic FPGA general logic primitive. Xilinx use LUT, Altera LE, microsemi/lattice possibly something else.

The problem is, they are not the same. In their most recent architecture, Xilinx use 6-input LUT and altera 4-input LUT. They are aggregated in logic blocks which has other features like fast-carry chain, registers and distributed memory.

Converting to system gates is useful, but don't forget it's also a marketing war. A Xilinx FPGA should fit 1.5 times the logic of an Altera FPGA, since it's LUT have 6 instead of 4, right? Well, it largely depends on the design, if the design can't use 6-inputs much, the unused ones are wasted. Same with fast-carry logic, I don't know if they count that in equivalent gate number, but be advised that number is inflated.

System gates is a common measure of ASIC design complexity. The same design on two different foundries should have similar system gates number, as waste is not really an issue for ASIC.

If you're looking for an FPGA. I suggest you choose your vendor, port enough of your design to get an idea of how big a FPGA you need and choose a FPGA with an upgrade path (if you want to market). If it's for a single prototype, just use the biggest FPGA you can afford. 

Logic array blocks (LABs) contain groups of LEs. 

Each LAB consists of the following features: 

■ 16 LEs

High-performance FPGA fabric Enhanced 8-input ALM with four registers 

The PCIe endpoint support includes multifunction support for up to eight functions, as shown in the following figure. The integrated multifunction support reduces the FPGA logic requirements by up to 20,000 LEs for PCIe designs that require multiple peripherals. 

Designing the ALM The ALM is radically different from any other FPGA logic block, offering a number of major innovations. Getting from a classic 4-LUT with a single register block (with associated carry logic) to the ALM required a detailed understanding of customer requirements and a large investment in researching the tradeoffs of various architectures. Our pursuit for a larger LUT was inspired by research results indicating that a basic 6-LUT could yield a 14% performance improvement by reducing the number of levels of logic elements on the critical paths of circuits. Unfortunately, this performance increase also had a large area penalty, a 17% area increase resulting from a larger LUT-mask and more inputs for the LUT. Figure 4 illustrates the tradeoff between cost and delay for different sizes of LUTs. The basic approach in designing the ALM was to investigate building a larger LUT to reduce levels of logic and increase performance, but to also avoid the area increase by efficiently dividing the larger LUT into smaller LUTs when appropriate, as illustrated by the dashed line. The ability to divide a LUT is what makes it “adaptive.”  

1장 악마라 불리는 사람들 15 

2장 공감의 뇌 과학 31 

3장 공감 제로의 두 얼굴: 부정적인 공감 제로 61 

4장 공감 제로의 두 얼굴: 긍정적인 공감 제로 119 

5장 공감 유전자 153 

6장 공감의 침식 뒤에 숨겨진 우리 안의 악마 177  

Device Family Support:

• • Virtex UltraScale 
   
  • Kintex UltraScale 
  • Zynq-7000 
   
  • Virtex-7 
   
  • Kintex-7 
   
  • Artix-7 
  • Spartan-6 
   
  • Virtex-6 
   
  • Virtex-5 
   
  • Virtex-4 
  • Spartan-3
   

Nios II/e[edit]

The Nios II/e core is designed for smallest possible logic utilization of FPGAs. This is especially efficient for low-cost Cyclone II FPGA applications. Features of Nios II/e include:

• Up to 2 GB of external address space
• JTAG debug module
• Complete systems in fewer than 700 LEs
• Optional debug enhancements
• Up to 256 custom instructions
• Free, no license required 

• The Cyclone IV GX FPGA architecture consists of up to 150K vertically arranged logic elements (LEs), 6.5 Mbits of embedded memory arranged as 9-Kbit (M9K) blocks, and 360 18 x 18 embedded multipliers. New to the Cyclone series, Cyclone IV GX FPGAs feature integrated transceivers at up to 3.125 Gbps.
• The Cyclone IV E FPGA architecture consists of up to 115K vertically arranged LEs, 4 Mbits of embedded memory arranged as 9-Kbit (M9K) blocks, and 266 18 x 18 embedded multipliers. 

FPGA Device

Altera Cyclone® V SE 5CSEMA4U23C6N device

HPS (Hard Processor System)

925MHz Dual-core ARM Cortex-A9 processor

1GB DDR3 SDRAM (32-bit data bus)

[링크 : https://www.terasic.com.tw/...&CategoryNo=167&No=941&PartNo=2]

Cyclone® IV EP4CE22F17C6N FPGA

22,320 Logic elements (LEs)

32MB SDRAM

2Kb I2C EEPROM 

G-Sensor ADI ADXL345, 3-axis accelerometer with high resolution (13-bit) 

A/D Converter NS ADC128S022, 8-Channel, 12-bit A/D Converter 50 ksps to 200 ksps 

Cyclone IV Device Family 

Features The Cyclone IV device family offers the following features: 

■ Low-cost, low-power FPGA fabric: 

■ 6K to 150K logic elements 

■ Up to 6.3 Mb of embedded memory 

■ Up to 360 18 × 18 multipliers for DSP processing intensive applications 

■ Protocol bridging applications for under 1.5 W total power 

Memory Modes Cyclone IV devices M9K memory blocks allow you to implement fully-synchronous SRAM memory in multiple modes of operation. Cyclone IV devices M9K memory blocks do not support asynchronous (unregistered) memory inputs.  

제14조(인공임신중절수술의 허용한계) ① 의사는 다음 각 호의 어느 하나에 해당되는 경우에만 본인과 배우자(사실상의 혼인관계에 있는 사람을 포함한다. 이하 같다)의 동의를 받아 인공임신중절수술을 할 수 있다.

1. 본인이나 배우자가 대통령령으로 정하는 우생학적(優生學的) 또는 유전학적 정신장애나 신체질환이 있는 경우

2. 본인이나 배우자가 대통령령으로 정하는 전염성 질환이 있는 경우

3. 강간 또는 준강간(準强姦)에 의하여 임신된 경우

4. 법률상 혼인할 수 없는 혈족 또는 인척 간에 임신된 경우

5. 임신의 지속이 보건의학적 이유로 모체의 건강을 심각하게 해치고 있거나 해칠 우려가 있는 경우

② 제1항의 경우에 배우자의 사망·실종·행방불명, 그 밖에 부득이한 사유로 동의를 받을 수 없으면 본인의 동의만으로 그 수술을 할 수 있다.

③ 제1항의 경우 본인이나 배우자가 심신장애로 의사표시를 할 수 없을 때에는 그 친권자나 후견인의 동의로, 친권자나 후견인이 없을 때에는 부양의무자의 동의로 각각 그 동의를 갈음할 수 있다.

[전문개정 2009.1.7.]

제28조(「형법」의 적용 배제) 이 법에 따른 인공임신중절수술을 받은 자와 수술을 한 자는 「형법」 제269조제1항·제2항 및 제270조제1항에도 불구하고 처벌하지 아니한다.

[전문개정 2009.1.7.]

제15조(인공임신중절수술의 허용한계) ① 법 제14조에 따른 인공임신중절수술은 임신 24주일 이내인 사람만 할 수 있다.

② 법 제14조제1항제1호에 따라 인공임신중절수술을 할 수 있는 우생학적 또는 유전학적 정신장애나 신체질환은 연골무형성증, 낭성섬유증 및 그 밖의 유전성 질환으로서 그 질환이 태아에 미치는 위험성이 높은 질환으로 한다.

③ 법 제14조제1항제2호에 따라 인공임신중절수술을 할 수 있는 전염성 질환은 풍진, 톡소플라즈마증 및 그 밖에 의학적으로 태아에 미치는 위험성이 높은 전염성 질환으로 한다.

[전문개정 2009.7.7.]