# cat /etc/postgresql/15/main/pg_hba.conf local all postgres peer
# TYPE DATABASE USER ADDRESS METHOD
# "local" is for Unix domain socket connections only local all all md5 # IPv4 local connections: host all all 127.0.0.1/32 scram-sha-256 # IPv6 local connections: host all all ::1/128 scram-sha-256 # Allow replication connections from localhost, by a user with the # replication privilege. local replication all peer host replication all 127.0.0.1/32 scram-sha-256 host replication all ::1/128 scram-sha-256
서비스 재기동
$ sudo systemctl restart postgresql
postgres 계정으로 로그인 후 계정 및 database 생성
pi@raspberrypi:~ $ sudo su - postgres postgres@raspberrypi:~$ psql psql (15.7 ( 15.7-0+deb12u1)) Type "help" for help.
postgres=# create user username with password 'userpassword'; CREATE ROLE postgres=# create database userdb; CREATE DATABASE materials=> \q postgres@raspberrypi:~$
일반 계정에서 특정 사용자로 로그인
pi@raspberrypi:~ $ psql -U username userdb Password for user username: psql (15.7 ( 15.7-0+deb12u1)) Type "help" for help.
Dual core • 32-bit Arm® Cortex®-M7 core with doubleprecision FPU and L1 cache: 16 Kbytes of data and 16 Kbytes of instruction cache; frequency up to 480 MHz, MPU, 1027 DMIPS/ 2.14 DMIPS/MHz (Dhrystone 2.1), and DSP instructions • 32-bit Arm® 32-bit Cortex®-M4 core with FPU, Adaptive real-time accelerator (ART Accelerator) for internal flash memory and external memories, frequency up to 240 MHz, MPU, 300 DMIPS/1.25 DMIPS /MHz (Dhrystone 2.1), and DSP instructions
ART 가속에 대해서는 머라머라 써있는데 이해를 못하겠고..
대충 온칩 메모리(SRAM)과 플래시에 대해서 대기없는 접근이 가능하다 정도로 이해..
그런데 Cortex-M4 에만 달려서 테시등을 확인하는걸 보면.. M4 쪽이 slave 구성인가 싶기도 하다
The acceleration is achieved by loading selected code into an embedded cache and making it instantly available to the Cortex-M4 core, thus avoiding latency due to memory wait states.
ART™ accelerator features: • 32-bit AHB slave port to interface with the D2 domain • 32-bit AHB master port for non-cacheable memory accesses • 64-bit AXI master port to load the code from memory to cache • 64 cache lines of 256 bits • Fully-associative cache • Programmable cacheable page • Cache content consistency checker
D1 domain 에는 cortex-M7이 있는 것 같고. M7 에만 TCM(tightly coupled memory)가 달려있다.
D2 domain 에는 Cortex-M4가 있고 플래시가 없다? D1 domain으로 접근해서 Flash에서 펌웨어를 불러오게 되는 구조 같다.
D3 domain 에는 DBMA / SDRAM 64k / Backup SRAM 4k 가 있는데 얘는 절전모드 용인가?
AHB는 1<->2<->3 그리고 1<->3 간에 존재하여 어느쪽이던 많이 돌지 않고 접근이 가능하다.
부팅은 BOOT0 핀과 BOOT_ADDx 옵션 바이트에 의해서 결정되는데
BOOT0 핀이 0이면
CM7은 플래시의 0x0800_000을 사용하고
CM4는 플래시의 0x0810_000을 사용한다.
BCM4/7은 SYSCFG_UR1 레지스터에 존재하는 녀석인데 얜 어느 시점에 누가 설정하지?
3.2 Dual-core boot At startup, the boot memory space is selected by the BOOT pin and BOOT_ADDx option bytes, allowing to program any boot memory address from 0x0000 0000 to 0x3FFF FFFF which includes all Flash address space, all RAM address space (ITCM, DTCM RAMs and SRAMs) and the System memory bootloader. The boot address is provided by option byte and default programmed value to allow: • CM7 Boots from Flash memory at 0x0800 0000 when Boot0=0 • CM4 Boots from Flash memory at 0x0810 0000 when Boot0=0 • Boot respectively from System memory or SRAM1 when Boot0=1 The values on the BOOT pin are latched on the 4th rising edge of SYSCLK after reset release. It is up to the user to set the BOOT pin after reset as shown in the figure below.
If the programmed boot memory address is out of the memory mapped area or a reserved area, the default boot fetch address is: • BCM7_ADD0: FLASH at 0x0800 0000 • BCM4_ADD0: FLASH at 0x0810 0000 • BCM7_ADD1: System Memory at 0x1FF0 0000 • BCM4_ADD1: SRAM1 at 0x1000 0000 When Flash level 2 protection is enabled, only boot from Flash or system is available. If boot address is out of the memory range or RAM address, then the default fetch is forced from Flash at address 0x0800 0000 for Cortex®‑M7 and Flash at address 0x0810 0000 for Cortex®-M4. In the STM32H7 dual‑core, to maximize energy efficiency, each core operates in its own power domain and can be turned off individually when not needed. The two cores can boot alone or in the same time according to the option bytes as shown in Table 4.
