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'잡동사니'에 해당되는 글 14133건
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Programming/qt2026. 3. 23. 12:30
embeded/FPGA - ALTERA2026. 3. 22. 22:33
2023년 6월 9일 단종 공고가 떴었다.
그럼 quartus도 22.x 까지만 지원할 것 같은데. 아예 사라진건진 봐야 알 듯.
[링크 : https://www.reddit.com/r/FPGA/comments/1492bx0/intel_discontinues_nios_ii_ip/]
nios v/m nios v/g 로 대체라면 기존의 ii/e ii/f 중에 f가 바뀌나?
ipr-nios가 정식으로 쓰는거고 ip-nios는 evaluation 이라는데(1시간 이후 멈춤) 맞나?
그나저나 DMIPS 드럽게 낮네
STM32F102x8 cortex-m3의 경우 1.25DMIPS 라는데 시기가 차이 있다 하더라도 nios ii/f가 제법 처참하다 싶다.
1.25 DMIPS/MHz (Dhrystone 2.1)
[링크 : https://www.st.com/resource/en/datasheet/stm32f102c8.pdf]
17년 이후로 Nios ii gen 2로 바뀌면서 nios ii/s는 사라지고 f만 남은거 같은데
그러면 위에 ip-nios랑 ipr-nios는 f인가? 머지?
Nios II classic is offered in 3 different configurations: Nios II/f (fast), Nios II/s (standard), and Nios II/e (economy). Nios II gen2 is offered in 2 different configurations: Nios II/f (fast), and Nios II/e (economy).Nios II/f
Nios II/s
Nios II/e |
[링크 : https://en.wikipedia.org/wiki/Nios_II]
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ai 답변
quartus 19.1 부터 EDS 제거되면서 윈도우에서 WSL 필요
quartus 24.1 부터 nios ii / eds 제거
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레딧도 그렇지만 정말 취미(?) 사용자를 위해서는 두 회사가 더 멀어지고 있지만
altera는 intel에 인수되면서 더 심화된것 같고. 그래서 altera가 다시 intel과 결별한게 아닌가 싶다.
[링크 : https://www.cio.com/article/3964395/인텔-알테라-지분-51-매각···-fpga-사업-정리해-구조-개.html]
이 추세면.. xilinx로 갈아타야 하려나.. 쩝..
terasic 형님들 de0-nano-soc 처럼 쌈박한 zynq 내주실 생각 없습니까!?!??!
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개소리 왈왈/육아관련 주저리2026. 3. 22. 17:57
찾아보니 원래 한 40만원 하던걸
비 맞고 수리비가 더 들어서 수리없이 5만원에 자전거 매장에서 중고로 업어옴
그래도 무려 티티카카 tube a7 이라 네임벨류가 있는 ㅋㅋ
embeded/FPGA - ALTERA2026. 3. 21. 23:50
아니.. HPS 넣으면 IP에서 추가하라고 말만하지 말고
좀 강하게 경고를 하라고 ㅠㅠ
quartus 에서 넣으면 되는줄 알았는데 그게 아니고
tools - platform designer 해서 넣어야 하나보다.(까먹어서 인터넷 검색..)
먼가 복잡하게 뜨는데 먼지 모르니 귀찮아서(!) finish 하고
clk 와 각종 clock_input들을 O를 클릭해서 검은색이 체크되어 클럭이 넘어오게 해주고
종료하려고 하면 Generate Now? 라고 물어보는데 이걸 "예" 하던가
platform designed의 우측 하단 Generate HDL을 누르면 될 듯.
그리고 Finish 해주면 먼가
아까는 안보이던 hps가 추가되어있는데
이걸 더블클릭해서 먼가 또 이상한짓을 하고 나면 되는 듯?
그리고 뜨는 다이얼로그를 보니 수동으로 추가해야 하나는 것 같다.
project nabigaor를 file로 하고 우클릭한다음 "Add/Remove Files in Project" 해서
설정 창이 열리면 File name ... 을 눌러서
qip 확장자를 찾아서 넣고
빌드해도 안되네!!!
아우 빡셔.. 튜토리얼 다시 찾아봐야겠다.
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지금은 Bidir로 되어있는데
이미 생성되어있는 프로젝트 열어서 보니 엥 Unknown?
readonly 라고 수정도 안되는데 어우.. 어떻게 하지 ㅠㅠ
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2026.03.22
아래껄 추가하니 조금더 진행은 되는데
| unnamed u0 ( .clk_clk ( CLOCK_50), // clk.clk .reset_reset_n ( 1'b1), // reset.reset_n .memory_mem_a ( HPS_DDR3_ADDR), // memory.mem_a .memory_mem_ba ( HPS_DDR3_BA), // .mem_ba .memory_mem_ck ( HPS_DDR3_CK_P), // .mem_ck .memory_mem_ck_n ( HPS_DDR3_CK_N), // .mem_ck_n .memory_mem_cke ( HPS_DDR3_CKE), // .mem_cke .memory_mem_cs_n ( HPS_DDR3_CS_N), // .mem_cs_n .memory_mem_ras_n ( HPS_DDR3_RAS_N), // .mem_ras_n .memory_mem_cas_n ( HPS_DDR3_CAS_N), // .mem_cas_n .memory_mem_we_n ( HPS_DDR3_WE_N), // .mem_we_n .memory_mem_reset_n ( HPS_DDR3_RESET_N), // .mem_reset_n .memory_mem_dq ( HPS_DDR3_DQ), // .mem_dq .memory_mem_dqs ( HPS_DDR3_DQS_P), // .mem_dqs .memory_mem_dqs_n ( HPS_DDR3_DQS_N), // .mem_dqs_n .memory_mem_odt ( HPS_DDR3_ODT), // .mem_odt .memory_mem_dm ( HPS_DDR3_DM), // .mem_dm .memory_oct_rzqin ( HPS_DDR3_RZQ), // .oct_rzqin }; |
또 먼가 잘못했는지 -_-
여전히 DDR3쪽 DQS 핀 에러는 여전하고
그 와중에 용량이 부족하다고 배째는데 이게 말이... 되나?
| Error (169008): Can't turn on open-drain option for differential I/O pin HPS_DDR3_DQS_N[1] Error (169008): Can't turn on open-drain option for differential I/O pin HPS_DDR3_DQS_N[2] Error (169008): Can't turn on open-drain option for differential I/O pin HPS_DDR3_DQS_N[3] Error (169008): Can't turn on open-drain option for differential I/O pin HPS_DDR3_DQS_P[1] Error (169008): Can't turn on open-drain option for differential I/O pin HPS_DDR3_DQS_P[2] Error (169008): Can't turn on open-drain option for differential I/O pin HPS_DDR3_DQS_P[3] Info (11798): Fitter preparation operations ending: elapsed time is 00:00:00 Warning (169064): Following 85 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results Info (169065): Pin AUD_ADCLRCK has a permanently disabled output enable Info (169065): Pin AUD_BCLK has a permanently disabled output enable Info (169065): Pin AUD_DACLRCK has a permanently disabled output enable Info (169065): Pin DRAM_DQ[0] has a permanently disabled output enable Info (169065): Pin DRAM_DQ[1] has a permanently disabled output enable Info (169065): Pin DRAM_DQ[2] has a permanently disabled output enable Info (169065): Pin DRAM_DQ[3] has a permanently disabled output enable Info (169065): Pin DRAM_DQ[4] has a permanently disabled output enable Info (169065): Pin DRAM_DQ[5] has a permanently disabled output enable Info (169065): Pin DRAM_DQ[6] has a permanently disabled output enable Info (169065): Pin DRAM_DQ[7] has a permanently disabled output enable Info (169065): Pin DRAM_DQ[8] has a permanently disabled output enable Info (169065): Pin DRAM_DQ[9] has a permanently disabled output enable Info (169065): Pin DRAM_DQ[10] has a permanently disabled output enable Info (169065): Pin DRAM_DQ[11] has a permanently disabled output enable Info (169065): Pin DRAM_DQ[12] has a permanently disabled output enable Info (169065): Pin DRAM_DQ[13] has a permanently disabled output enable Info (169065): Pin DRAM_DQ[14] has a permanently disabled output enable Info (169065): Pin DRAM_DQ[15] has a permanently disabled output enable Info (169065): Pin FPGA_I2C_SDAT has a permanently disabled output enable Info (169065): Pin PS2_CLK has a permanently disabled output enable Info (169065): Pin PS2_CLK2 has a permanently disabled output enable Info (169065): Pin PS2_DAT has a permanently disabled output enable Info (169065): Pin PS2_DAT2 has a permanently disabled output enable Info (169065): Pin HPS_CONV_USB_N has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[8] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[9] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[10] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[11] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[12] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[13] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[14] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[15] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[16] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[17] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[18] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[19] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[20] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[21] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[22] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[23] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[24] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[25] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[26] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[27] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[28] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[29] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[30] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[31] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQS_N[1] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQS_N[2] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQS_N[3] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQS_P[1] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQS_P[2] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQS_P[3] has a permanently disabled output enable Info (169065): Pin HPS_ENET_INT_N has a permanently disabled output enable Info (169065): Pin HPS_ENET_MDIO has a permanently disabled output enable Info (169065): Pin HPS_FLASH_DATA[0] has a permanently disabled output enable Info (169065): Pin HPS_FLASH_DATA[1] has a permanently disabled output enable Info (169065): Pin HPS_FLASH_DATA[2] has a permanently disabled output enable Info (169065): Pin HPS_FLASH_DATA[3] has a permanently disabled output enable Info (169065): Pin HPS_GPIO[0] has a permanently disabled output enable Info (169065): Pin HPS_GPIO[1] has a permanently disabled output enable Info (169065): Pin HPS_GSENSOR_INT has a permanently disabled output enable Info (169065): Pin HPS_I2C1_SCLK has a permanently disabled output enable Info (169065): Pin HPS_I2C1_SDAT has a permanently disabled output enable Info (169065): Pin HPS_I2C2_SCLK has a permanently disabled output enable Info (169065): Pin HPS_I2C2_SDAT has a permanently disabled output enable Info (169065): Pin HPS_I2C_CONTROL has a permanently disabled output enable Info (169065): Pin HPS_KEY has a permanently disabled output enable Info (169065): Pin HPS_LED has a permanently disabled output enable Info (169065): Pin HPS_SD_CMD has a permanently disabled output enable Info (169065): Pin HPS_SD_DATA[0] has a permanently disabled output enable Info (169065): Pin HPS_SD_DATA[1] has a permanently disabled output enable Info (169065): Pin HPS_SD_DATA[2] has a permanently disabled output enable Info (169065): Pin HPS_SD_DATA[3] has a permanently disabled output enable Info (169065): Pin HPS_SPIM_SS has a permanently disabled output enable Info (169065): Pin HPS_USB_DATA[0] has a permanently disabled output enable Info (169065): Pin HPS_USB_DATA[1] has a permanently disabled output enable Info (169065): Pin HPS_USB_DATA[2] has a permanently disabled output enable Info (169065): Pin HPS_USB_DATA[3] has a permanently disabled output enable Info (169065): Pin HPS_USB_DATA[4] has a permanently disabled output enable Info (169065): Pin HPS_USB_DATA[5] has a permanently disabled output enable Info (169065): Pin HPS_USB_DATA[6] has a permanently disabled output enable Info (169065): Pin HPS_USB_DATA[7] has a permanently disabled output enable Warning (169069): Following 216 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results Info (169070): Pin ADC_CONVST has GND driving its datain port Info (169070): Pin ADC_DIN has GND driving its datain port Info (169070): Pin ADC_SCLK has GND driving its datain port Info (169070): Pin AUD_DACDAT has GND driving its datain port Info (169070): Pin AUD_XCK has GND driving its datain port Info (169070): Pin DRAM_ADDR[0] has GND driving its datain port Info (169070): Pin DRAM_ADDR[1] has GND driving its datain port Info (169070): Pin DRAM_ADDR[2] has GND driving its datain port Info (169070): Pin DRAM_ADDR[3] has GND driving its datain port Info (169070): Pin DRAM_ADDR[4] has GND driving its datain port Info (169070): Pin DRAM_ADDR[5] has GND driving its datain port Info (169070): Pin DRAM_ADDR[6] has GND driving its datain port Info (169070): Pin DRAM_ADDR[7] has GND driving its datain port Info (169070): Pin DRAM_ADDR[8] has GND driving its datain port Info (169070): Pin DRAM_ADDR[9] has GND driving its datain port Info (169070): Pin DRAM_ADDR[10] has GND driving its datain port Info (169070): Pin DRAM_ADDR[11] has GND driving its datain port Info (169070): Pin DRAM_ADDR[12] has GND driving its datain port Info (169070): Pin DRAM_BA[0] has GND driving its datain port Info (169070): Pin DRAM_BA[1] has GND driving its datain port Info (169070): Pin DRAM_CAS_N has GND driving its datain port Info (169070): Pin DRAM_CKE has GND driving its datain port Info (169070): Pin DRAM_CLK has GND driving its datain port Info (169070): Pin DRAM_CS_N has GND driving its datain port Info (169070): Pin DRAM_LDQM has GND driving its datain port Info (169070): Pin DRAM_RAS_N has GND driving its datain port Info (169070): Pin DRAM_UDQM has GND driving its datain port Info (169070): Pin DRAM_WE_N has GND driving its datain port Info (169070): Pin FPGA_I2C_SCLK has GND driving its datain port Info (169070): Pin HEX0[0] has GND driving its datain port Info (169070): Pin HEX0[1] has GND driving its datain port Info (169070): Pin HEX0[2] has GND driving its datain port Info (169070): Pin HEX0[3] has GND driving its datain port Info (169070): Pin HEX0[4] has GND driving its datain port Info (169070): Pin HEX0[5] has GND driving its datain port Info (169070): Pin HEX0[6] has GND driving its datain port Info (169070): Pin HEX1[0] has GND driving its datain port Info (169070): Pin HEX1[1] has GND driving its datain port Info (169070): Pin HEX1[2] has GND driving its datain port Info (169070): Pin HEX1[3] has GND driving its datain port Info (169070): Pin HEX1[4] has GND driving its datain port Info (169070): Pin HEX1[5] has GND driving its datain port Info (169070): Pin HEX1[6] has GND driving its datain port Info (169070): Pin HEX2[0] has GND driving its datain port Info (169070): Pin HEX2[1] has GND driving its datain port Info (169070): Pin HEX2[2] has GND driving its datain port Info (169070): Pin HEX2[3] has GND driving its datain port Info (169070): Pin HEX2[4] has GND driving its datain port Info (169070): Pin HEX2[5] has GND driving its datain port Info (169070): Pin HEX2[6] has GND driving its datain port Info (169070): Pin HEX3[0] has GND driving its datain port Info (169070): Pin HEX3[1] has GND driving its datain port Info (169070): Pin HEX3[2] has GND driving its datain port Info (169070): Pin HEX3[3] has GND driving its datain port Info (169070): Pin HEX3[4] has GND driving its datain port Info (169070): Pin HEX3[5] has GND driving its datain port Info (169070): Pin HEX3[6] has GND driving its datain port Info (169070): Pin HEX4[0] has GND driving its datain port Info (169070): Pin HEX4[1] has GND driving its datain port Info (169070): Pin HEX4[2] has GND driving its datain port Info (169070): Pin HEX4[3] has GND driving its datain port Info (169070): Pin HEX4[4] has GND driving its datain port Info (169070): Pin HEX4[5] has GND driving its datain port Info (169070): Pin HEX4[6] has GND driving its datain port Info (169070): Pin HEX5[0] has GND driving its datain port Info (169070): Pin HEX5[1] has GND driving its datain port Info (169070): Pin HEX5[2] has GND driving its datain port Info (169070): Pin HEX5[3] has GND driving its datain port Info (169070): Pin HEX5[4] has GND driving its datain port Info (169070): Pin HEX5[5] has GND driving its datain port Info (169070): Pin HEX5[6] has GND driving its datain port Info (169070): Pin IRDA_TXD has GND driving its datain port Info (169070): Pin LEDR[0] has GND driving its datain port Info (169070): Pin LEDR[1] has GND driving its datain port Info (169070): Pin LEDR[2] has GND driving its datain port Info (169070): Pin LEDR[3] has GND driving its datain port Info (169070): Pin LEDR[4] has GND driving its datain port Info (169070): Pin LEDR[5] has GND driving its datain port Info (169070): Pin LEDR[6] has GND driving its datain port Info (169070): Pin LEDR[7] has GND driving its datain port Info (169070): Pin LEDR[8] has GND driving its datain port Info (169070): Pin LEDR[9] has GND driving its datain port Info (169070): Pin TD_RESET_N has GND driving its datain port Info (169070): Pin VGA_BLANK_N has GND driving its datain port Info (169070): Pin VGA_B[0] has GND driving its datain port Info (169070): Pin VGA_B[1] has GND driving its datain port Info (169070): Pin VGA_B[2] has GND driving its datain port Info (169070): Pin VGA_B[3] has GND driving its datain port Info (169070): Pin VGA_B[4] has GND driving its datain port Info (169070): Pin VGA_B[5] has GND driving its datain port Info (169070): Pin VGA_B[6] has GND driving its datain port Info (169070): Pin VGA_B[7] has GND driving its datain port Info (169070): Pin VGA_CLK has GND driving its datain port Info (169070): Pin VGA_G[0] has GND driving its datain port Info (169070): Pin VGA_G[1] has GND driving its datain port Info (169070): Pin VGA_G[2] has GND driving its datain port Info (169070): Pin VGA_G[3] has GND driving its datain port Info (169070): Pin VGA_G[4] has GND driving its datain port Info (169070): Pin VGA_G[5] has GND driving its datain port Info (169070): Pin VGA_G[6] has GND driving its datain port Info (169070): Pin VGA_G[7] has GND driving its datain port Info (169070): Pin VGA_HS has GND driving its datain port Info (169070): Pin VGA_R[0] has GND driving its datain port Info (169070): Pin VGA_R[1] has GND driving its datain port Info (169070): Pin VGA_R[2] has GND driving its datain port Info (169070): Pin VGA_R[3] has GND driving its datain port Info (169070): Pin VGA_R[4] has GND driving its datain port Info (169070): Pin VGA_R[5] has GND driving its datain port Info (169070): Pin VGA_R[6] has GND driving its datain port Info (169070): Pin VGA_R[7] has GND driving its datain port Info (169070): Pin VGA_SYNC_N has GND driving its datain port Info (169070): Pin VGA_VS has GND driving its datain port Info (169070): Pin HPS_DDR3_ADDR[13] has GND driving its datain port Info (169070): Pin HPS_DDR3_ADDR[14] has GND driving its datain port Info (169070): Pin HPS_DDR3_DM[1] has GND driving its datain port Info (169070): Pin HPS_DDR3_DM[2] has GND driving its datain port Info (169070): Pin HPS_DDR3_DM[3] has GND driving its datain port Info (169070): Pin HPS_ENET_GTX_CLK has GND driving its datain port Info (169070): Pin HPS_ENET_MDC has GND driving its datain port Info (169070): Pin HPS_ENET_TX_DATA[0] has GND driving its datain port Info (169070): Pin HPS_ENET_TX_DATA[1] has GND driving its datain port Info (169070): Pin HPS_ENET_TX_DATA[2] has GND driving its datain port Info (169070): Pin HPS_ENET_TX_DATA[3] has GND driving its datain port Info (169070): Pin HPS_ENET_TX_EN has GND driving its datain port Info (169070): Pin HPS_FLASH_DCLK has GND driving its datain port Info (169070): Pin HPS_FLASH_NCSO has GND driving its datain port Info (169070): Pin HPS_SD_CLK has GND driving its datain port Info (169070): Pin HPS_SPIM_CLK has GND driving its datain port Info (169070): Pin HPS_SPIM_MOSI has GND driving its datain port Info (169070): Pin HPS_UART_TX has GND driving its datain port Info (169070): Pin HPS_USB_STP has GND driving its datain port Info (169070): Pin AUD_ADCLRCK has VCC driving its datain port Info (169070): Pin AUD_BCLK has VCC driving its datain port Info (169070): Pin AUD_DACLRCK has VCC driving its datain port Info (169070): Pin DRAM_DQ[0] has VCC driving its datain port Info (169070): Pin DRAM_DQ[1] has VCC driving its datain port Info (169070): Pin DRAM_DQ[2] has VCC driving its datain port Info (169070): Pin DRAM_DQ[3] has VCC driving its datain port Info (169070): Pin DRAM_DQ[4] has VCC driving its datain port Info (169070): Pin DRAM_DQ[5] has VCC driving its datain port Info (169070): Pin DRAM_DQ[6] has VCC driving its datain port Info (169070): Pin DRAM_DQ[7] has VCC driving its datain port Info (169070): Pin DRAM_DQ[8] has VCC driving its datain port Info (169070): Pin DRAM_DQ[9] has VCC driving its datain port Info (169070): Pin DRAM_DQ[10] has VCC driving its datain port Info (169070): Pin DRAM_DQ[11] has VCC driving its datain port Info (169070): Pin DRAM_DQ[12] has VCC driving its datain port Info (169070): Pin DRAM_DQ[13] has VCC driving its datain port Info (169070): Pin DRAM_DQ[14] has VCC driving its datain port Info (169070): Pin DRAM_DQ[15] has VCC driving its datain port Info (169070): Pin FPGA_I2C_SDAT has VCC driving its datain port Info (169070): Pin PS2_CLK has VCC driving its datain port Info (169070): Pin PS2_CLK2 has VCC driving its datain port Info (169070): Pin PS2_DAT has VCC driving its datain port Info (169070): Pin PS2_DAT2 has VCC driving its datain port Info (169070): Pin HPS_CONV_USB_N has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[8] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[9] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[10] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[11] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[12] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[13] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[14] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[15] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[16] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[17] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[18] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[19] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[20] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[21] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[22] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[23] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[24] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[25] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[26] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[27] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[28] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[29] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[30] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[31] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQS_N[1] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQS_N[2] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQS_N[3] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQS_P[1] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQS_P[2] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQS_P[3] has VCC driving its datain port Info (169070): Pin HPS_ENET_INT_N has VCC driving its datain port Info (169070): Pin HPS_ENET_MDIO has VCC driving its datain port Info (169070): Pin HPS_FLASH_DATA[0] has VCC driving its datain port Info (169070): Pin HPS_FLASH_DATA[1] has VCC driving its datain port Info (169070): Pin HPS_FLASH_DATA[2] has VCC driving its datain port Info (169070): Pin HPS_FLASH_DATA[3] has VCC driving its datain port Info (169070): Pin HPS_GPIO[0] has VCC driving its datain port Info (169070): Pin HPS_GPIO[1] has VCC driving its datain port Info (169070): Pin HPS_GSENSOR_INT has VCC driving its datain port Info (169070): Pin HPS_I2C1_SCLK has VCC driving its datain port Info (169070): Pin HPS_I2C1_SDAT has VCC driving its datain port Info (169070): Pin HPS_I2C2_SCLK has VCC driving its datain port Info (169070): Pin HPS_I2C2_SDAT has VCC driving its datain port Info (169070): Pin HPS_I2C_CONTROL has VCC driving its datain port Info (169070): Pin HPS_KEY has VCC driving its datain port Info (169070): Pin HPS_LED has VCC driving its datain port Info (169070): Pin HPS_SD_CMD has VCC driving its datain port Info (169070): Pin HPS_SD_DATA[0] has VCC driving its datain port Info (169070): Pin HPS_SD_DATA[1] has VCC driving its datain port Info (169070): Pin HPS_SD_DATA[2] has VCC driving its datain port Info (169070): Pin HPS_SD_DATA[3] has VCC driving its datain port Info (169070): Pin HPS_SPIM_SS has VCC driving its datain port Info (169070): Pin HPS_USB_DATA[0] has VCC driving its datain port Info (169070): Pin HPS_USB_DATA[1] has VCC driving its datain port Info (169070): Pin HPS_USB_DATA[2] has VCC driving its datain port Info (169070): Pin HPS_USB_DATA[3] has VCC driving its datain port Info (169070): Pin HPS_USB_DATA[4] has VCC driving its datain port Info (169070): Pin HPS_USB_DATA[5] has VCC driving its datain port Info (169070): Pin HPS_USB_DATA[6] has VCC driving its datain port Info (169070): Pin HPS_USB_DATA[7] has VCC driving its datain port Info (169186): Following groups of pins have the same dynamic on-chip termination control Info (169185): Following pins have the same dynamic on-chip termination control: unnamed:u0|unnamed_hps_0:hps_0|unnamed_hps_0_hps_0:hps_0|unnamed_hps_0_hps_0_hps_io:hps_io|unnamed_hps_0_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|diff_dtc_bar Info (169066): Type bi-directional pin HPS_DDR3_DQS_N[0] uses the Differential 1.5-V SSTL Class I I/O standard Info (169185): Following pins have the same dynamic on-chip termination control: unnamed:u0|unnamed_hps_0:hps_0|unnamed_hps_0_hps_0:hps_0|unnamed_hps_0_hps_0_hps_io:hps_io|unnamed_hps_0_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin HPS_DDR3_DQ[0] uses the SSTL-15 Class I I/O standard Info (169185): Following pins have the same dynamic on-chip termination control: unnamed:u0|unnamed_hps_0:hps_0|unnamed_hps_0_hps_0:hps_0|unnamed_hps_0_hps_0_hps_io:hps_io|unnamed_hps_0_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin HPS_DDR3_DQ[1] uses the SSTL-15 Class I I/O standard Info (169185): Following pins have the same dynamic on-chip termination control: unnamed:u0|unnamed_hps_0:hps_0|unnamed_hps_0_hps_0:hps_0|unnamed_hps_0_hps_0_hps_io:hps_io|unnamed_hps_0_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin HPS_DDR3_DQ[2] uses the SSTL-15 Class I I/O standard Info (169185): Following pins have the same dynamic on-chip termination control: unnamed:u0|unnamed_hps_0:hps_0|unnamed_hps_0_hps_0:hps_0|unnamed_hps_0_hps_0_hps_io:hps_io|unnamed_hps_0_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin HPS_DDR3_DQ[3] uses the SSTL-15 Class I I/O standard Info (169185): Following pins have the same dynamic on-chip termination control: unnamed:u0|unnamed_hps_0:hps_0|unnamed_hps_0_hps_0:hps_0|unnamed_hps_0_hps_0_hps_io:hps_io|unnamed_hps_0_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin HPS_DDR3_DQ[4] uses the SSTL-15 Class I I/O standard Info (169185): Following pins have the same dynamic on-chip termination control: unnamed:u0|unnamed_hps_0:hps_0|unnamed_hps_0_hps_0:hps_0|unnamed_hps_0_hps_0_hps_io:hps_io|unnamed_hps_0_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin HPS_DDR3_DQ[5] uses the SSTL-15 Class I I/O standard Info (169185): Following pins have the same dynamic on-chip termination control: unnamed:u0|unnamed_hps_0:hps_0|unnamed_hps_0_hps_0:hps_0|unnamed_hps_0_hps_0_hps_io:hps_io|unnamed_hps_0_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin HPS_DDR3_DQ[6] uses the SSTL-15 Class I I/O standard Info (169185): Following pins have the same dynamic on-chip termination control: unnamed:u0|unnamed_hps_0:hps_0|unnamed_hps_0_hps_0:hps_0|unnamed_hps_0_hps_0_hps_io:hps_io|unnamed_hps_0_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin HPS_DDR3_DQ[7] uses the SSTL-15 Class I I/O standard Info (169185): Following pins have the same dynamic on-chip termination control: unnamed:u0|unnamed_hps_0:hps_0|unnamed_hps_0_hps_0:hps_0|unnamed_hps_0_hps_0_hps_io:hps_io|unnamed_hps_0_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|diff_dtc Info (169066): Type bi-directional pin HPS_DDR3_DQS_P[0] uses the Differential 1.5-V SSTL Class I I/O standard Error (11802): Can't fit design in device. Modify your design to reduce resources, or choose a larger device. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. Error: Quartus Prime Fitter was unsuccessful. 7 errors, 5 warnings Error: Peak virtual memory: 5113 megabytes Error: Processing ended: Sun Mar 22 17:55:31 2026 Error: Elapsed time: 00:00:06 Error: Total CPU time (on all processors): 00:00:05 Error (293001): Quartus Prime Full Compilation was unsuccessful. 9 errors, 341 warnings |
로직이 부족한줄 알았는데 핀이 너무 많이 할당되어도 그런 에러가 발생하는 건가?
[링크 : https://stackoverflow.com/questions/50442061/quartus-unable-to-fit-design-to-device]
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embeded/jetson2026. 3. 20. 21:40
회사에서는 멀티 충전기로 했어서 그런가 wifi 꽂고나서는 안켜지던데
집에서 5V 2A 짜리 단독으로 물리니 문제없이 작동한다.
인터넷 찾아봐도 소비전력 이야기가 딱히 없던데(몇 mW 라던가..) 그냥 그러려니 하고 써야하나?
| $ ifconfig docker0: flags=4099<UP,BROADCAST,MULTICAST> mtu 1500 inet 172.17.0.1 netmask 255.255.0.0 broadcast 172.17.255.255 ether 02:42:58:b4:8a:df txqueuelen 0 (Ethernet) RX packets 0 bytes 0 (0.0 B) RX errors 0 dropped 0 overruns 0 frame 0 TX packets 0 bytes 0 (0.0 B) TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0 eth0: flags=4099<UP,BROADCAST,MULTICAST> mtu 1500 ether 00:04:4b:e5:59:5d txqueuelen 1000 (Ethernet) RX packets 0 bytes 0 (0.0 B) RX errors 0 dropped 0 overruns 0 frame 0 TX packets 0 bytes 0 (0.0 B) TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0 device interrupt 150 base 0xc000 lo: flags=73<UP,LOOPBACK,RUNNING> mtu 65536 inet 127.0.0.1 netmask 255.0.0.0 inet6 ::1 prefixlen 128 scopeid 0x10<host> loop txqueuelen 1 (Local Loopback) RX packets 112 bytes 9000 (9.0 KB) RX errors 0 dropped 0 overruns 0 frame 0 TX packets 112 bytes 9000 (9.0 KB) TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0 rndis0: flags=4099<UP,BROADCAST,MULTICAST> mtu 1500 ether aa:be:7b:09:f3:5d txqueuelen 1000 (Ethernet) RX packets 0 bytes 0 (0.0 B) RX errors 0 dropped 0 overruns 0 frame 0 TX packets 0 bytes 0 (0.0 B) TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0 usb0: flags=4099<UP,BROADCAST,MULTICAST> mtu 1500 ether aa:be:7b:09:f3:5f txqueuelen 1000 (Ethernet) RX packets 0 bytes 0 (0.0 B) RX errors 0 dropped 0 overruns 0 frame 0 TX packets 0 bytes 0 (0.0 B) TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0 wlan0: flags=4099<UP,BROADCAST,MULTICAST> mtu 1500 ether 74:d8:3e:44:9f:17 txqueuelen 1000 (Ethernet) RX packets 0 bytes 0 (0.0 B) RX errors 0 dropped 0 overruns 0 frame 0 TX packets 0 bytes 0 (0.0 B) TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0 |
| $ lspci -t -v -[0000:00]-+-01.0-[01]----00.0 Intel Corporation Wireless 8265 / 8275 \-02.0-[02]----00.0 Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller $ lspci 00:01.0 PCI bridge: NVIDIA Corporation Device 0fae (rev a1) 00:02.0 PCI bridge: NVIDIA Corporation Device 0faf (rev a1) 01:00.0 Network controller: Intel Corporation Wireless 8265 / 8275 (rev 78) 02:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller (rev 15) $ lspci -v 00:01.0 PCI bridge: NVIDIA Corporation Device 0fae (rev a1) (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0, IRQ 84 Bus: primary=00, secondary=01, subordinate=01, sec-latency=0 Memory behind bridge: 13000000-130fffff Capabilities: </access denied> Kernel driver in use: pcieport 00:02.0 PCI bridge: NVIDIA Corporation Device 0faf (rev a1) (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0, IRQ 84 Bus: primary=00, secondary=02, subordinate=02, sec-latency=0 I/O behind bridge: 00001000-00001fff Memory behind bridge: 13100000-131fffff Capabilities: </access denied> Kernel driver in use: pcieport 01:00.0 Network controller: Intel Corporation Wireless 8265 / 8275 (rev 78) Subsystem: Intel Corporation Dual Band Wireless-AC 8265 Flags: bus master, fast devsel, latency 0, IRQ 408 Memory at 13000000 (64-bit, non-prefetchable) [size=8K] Capabilities: </access denied> Kernel driver in use: iwlwifi Kernel modules: iwlwifi 02:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller (rev 15) Subsystem: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller Flags: bus master, fast devsel, latency 0, IRQ 406 I/O ports at 1000 [size=256] Memory at 13104000 (64-bit, non-prefetchable) [size=4K] Memory at 13100000 (64-bit, non-prefetchable) [size=16K] Capabilities: </access denied> Kernel driver in use: r8168 |
mini-pciex도 아니고 왜 m.2로 만드는진 모르겠지만
아무튼 m.2 폼팩터의 무선랜이고
i-pex의 MHF4 (혹은 ipex4라고 표기) 커넥터의 듀얼 안테나 제품이다.
랜카드가 7천원 + 3천인데
[링크 : https://itempage3.auction.co.kr/DetailView.aspx?itemno=F310755633]
MHF4가 2800원 + 3천원. 배보다 배꼽이 더 큰 느낌이고
그 와중에 저건 또 케이블이라 SMA 2.4GHz 안테나가 필요하다는 것 이 또 추가지출을 하게 하네..
(회사에서 뽀려야지 -_-)
[링크 : https://itempage3.auction.co.kr/DetailView.aspx?itemno=E598839737]
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embeded/jetson2026. 3. 20. 19:12
버전 차이가 있긴 한데
jetcard가 용량이 제법늘어나 있다.
보드리비전만 따지고 모듈 리비전은 안따지나?
[링크 : https://github.com/NVIDIA-AI-IOT/jetcard]
[링크 : https://m.blog.naver.com/zeta0807/221934764603]
[링크 : https://m.blog.naver.com/zeta0807/222043543005]
+
2026.03.21
jetcard로 굽고나서 부팅하니 먼가 뜨는데 안된다.
그래서 하라는대로 하려는데 이 미묘한(?) 함정은 멀까 ㅋㅋ
메모리 부족하니 이런거 설정해라 라고 하는데 실제로는 퍼미션에러 ㅋㅋㅋ
| $ jupyter lab build /usr/lib/python3/dist-packages/requests/__init__.py:80: RequestsDependencyWarning: urllib3 (1.26.4) or chardet (3.0.4) doesn't match a supported version! RequestsDependencyWarning) [LabBuildApp] JupyterLab 2.2.6 [LabBuildApp] Building in /usr/local/share/jupyter/lab [LabBuildApp] Building jupyterlab assets (build:dev:minimize) Build failed. Troubleshooting: If the build failed due to an out-of-memory error, you may be able to fix it by disabling the `dev_build` and/or `minimize` options. If you are building via the `jupyter lab build` command, you can disable these options like so: jupyter lab build --dev-build=False --minimize=False You can also disable these options for all JupyterLab builds by adding these lines to a Jupyter config file named `jupyter_config.py`: c.LabBuildApp.minimize = False c.LabBuildApp.dev_build = False If you don't already have a `jupyter_config.py` file, you can create one by adding a blank file of that name to any of the Jupyter config directories. The config directories can be listed by running: jupyter --paths Explanation: - `dev-build`: This option controls whether a `dev` or a more streamlined `production` build is used. This option will default to `False` (ie the `production` build) for most users. However, if you have any labextensions installed from local files, this option will instead default to `True`. Explicitly setting `dev-build` to `False` will ensure that the `production` build is used in all circumstances. - `minimize`: This option controls whether your JS bundle is minified during the Webpack build, which helps to improve JupyterLab's overall performance. However, the minifier plugin used by Webpack is very memory intensive, so turning it off may help the build finish successfully in low-memory environments. An error occured. PermissionError: [Errno 13] Permission denied: '/usr/local/share/jupyter/lab/staging/index.js' See the log file for details: /tmp/jupyterlab-debug-nd1103ww.log |
기본 패스워드는 jetson이다.
아무튼 잘 빌드된다. 역시 4GB!
| $ sudo jupyter lab build [sudo] password for jetson: /usr/lib/python3/dist-packages/requests/__init__.py:80: RequestsDependencyWarning: urllib3 (1.26.4) or chardet (3.0.4) doesn't match a supported version! RequestsDependencyWarning) [LabBuildApp] JupyterLab 2.2.6 [LabBuildApp] Building in /usr/local/share/jupyter/lab [LabBuildApp] Building jupyterlab assets (build:dev:minimize) |
메모리 더 확보하려고 X 죽이려고 하는데 안네.. (gdm, gdm3 stop으로는 안됨)
역시 single user로 해야하나..
| $ free -h total used free shared buff/cache available Mem: 3.9G 630M 2.7G 28M 545M 3.1G Swap: 5.9G 0B 5.9G |
아까는 disable 안하고 stop만 해서 그런가?
아무튼 약 140MB 더 확보가 가능하다.
| $ sudo systemctl disable gdm3 [sudo] password for jetson: Synchronizing state of gdm3.service with SysV service script with /lib/systemd/systemd-sysv-install. Executing: /lib/systemd/systemd-sysv-install disable gdm3 $ free -h total used free shared buff/cache available Mem: 3.9G 619M 2.7G 28M 546M 3.1G Swap: 5.9G 0B 5.9G $ sudo systemctl stop gdm3 $ free -h total used free shared buff/cache available Mem: 3.9G 475M 2.9G 27M 545M 3.3G Swap: 5.9G 0B 5.9G |
주피터 접속하니 475MB 에서 순간 769MB 까지 증가하더니 595MB로 줄어든다.
2기가 에서는 gdm 꺼도 스왑쓰지 않으면 위험할지도?
| $ free -h total used free shared buff/cache available Mem: 3.9G 475M 2.9G 27M 545M 3.3G Swap: 5.9G 0B 5.9G $ free -h total used free shared buff/cache available Mem: 3.9G 517M 2.8G 27M 555M 3.3G Swap: 5.9G 0B 5.9G $ free -h total used free shared buff/cache available Mem: 3.9G 570M 2.8G 27M 559M 3.2G Swap: 5.9G 0B 5.9G $ free -h total used free shared buff/cache available Mem: 3.9G 525M 2.8G 27M 561M 3.3G Swap: 5.9G 0B 5.9G $ free -h total used free shared buff/cache available Mem: 3.9G 543M 2.8G 27M 562M 3.3G Swap: 5.9G 0B 5.9G $ free -h total used free shared buff/cache available Mem: 3.9G 614M 2.7G 27M 563M 3.2G Swap: 5.9G 0B 5.9G $ free -h total used free shared buff/cache available Mem: 3.9G 666M 2.7G 27M 563M 3.1G Swap: 5.9G 0B 5.9G $ free -h total used free shared buff/cache available Mem: 3.9G 722M 2.6G 27M 564M 3.1G Swap: 5.9G 0B 5.9G $ free -h total used free shared buff/cache available Mem: 3.9G 747M 2.6G 27M 564M 3.1G Swap: 5.9G 0B 5.9G $ free -h total used free shared buff/cache available Mem: 3.9G 769M 2.6G 27M 567M 3.0G Swap: 5.9G 0B 5.9G $ free -h total used free shared buff/cache available Mem: 3.9G 602M 2.7G 27M 567M 3.2G Swap: 5.9G 0B 5.9G $ free -h total used free shared buff/cache available Mem: 3.9G 607M 2.7G 27M 567M 3.2G Swap: 5.9G 0B 5.9G $ free -h total used free shared buff/cache available Mem: 3.9G 607M 2.7G 27M 567M 3.2G Swap: 5.9G 0B 5.9G $ free -h total used free shared buff/cache available Mem: 3.9G 595M 2.7G 27M 567M 3.2G Swap: 5.9G 0B 5.9G |
[링크 : https://eteo.tistory.com/997]
[링크 : https://forums.developer.nvidia.com/t/disabling-the-desktop-gui/257951]
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Programming/qt2026. 3. 19. 16:00
화면에서는 Next 이런게 나오는데 소스에는 없어서 열어보니 QWizard 라는 클래스를 사용중이라 조사.
setTitle로 상단에 표시되는 항목이 지정되고
실제 내용이 label 을 통해 별도로 추가된다.
| QWizardPage *createIntroPage() { QWizardPage *page = new QWizardPage; page->setTitle("Introduction"); QLabel *label = new QLabel("This wizard will help you register your copy " "of Super Product Two."); label->setWordWrap(true); QVBoxLayout *layout = new QVBoxLayout; layout->addWidget(label); page->setLayout(layout); return page; } |
위저드를 써서 그런가 엄청 심플해진다.
| QWizard wizard; wizard.addPage(createIntroPage()); wizard.addPage(createRegistrationPage()); wizard.addPage(createConclusionPage()); //! [linearAddPage] wizard.setWindowTitle("Trivial Wizard"); wizard.show(); |
[링크 : https://doc.qt.io/qt-6/qtwidgets-dialogs-trivialwizard-example.html]
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하드웨어/커넥터 (Connector)2026. 3. 19. 15:41
i-pex는 회사 이름이자 브랜드 명이라고 한다.
| 그 일환으로서, 기업이 바라보는 모습을 명시함과 함께, 글로벌 브랜드 인지도의 확대를 도모하기 위해 2020년 8월부터 사명과 브랜드를 [I-PEX(아이펙스)]로 통일했습니다. 앞으로도 그룹의 모든 임직원이 [I-PEX] 아래 하나가 되어, 독자적인 기술,상품,솔루션을 제공하여 세계에서 신뢰받고 사랑받는 글로벌 브랜드로 성장시켜 나가겠습니다. I-PEX = Innovative Product development & Engineering solutions eXpert |
[링크 : https://www.i-pex.com/ko-kr/who-we-are]
아무튼 회사에서 평범하게 보던게 MHF1 인것 같은데
intel 8265ngw m.2 무선랜카드의 커넥터에 꽂아지지 않길래 찾아보니
ipex인건 맞는데 MHF 라는 다른(?) 명칭이 더 있다고..
[링크 : https://m.blog.naver.com/just4u78/222131170259]
i-pex MHF 4L이 M.2의 표준인데 1.2mm 와 1.4mm 두가지를 허용하나보다.
[링크 : https://www.i-pex.com/sites/default/files/pdf/Matrix_RF_Connector_E.pdf]
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embeded/Cortex-M4 STM2026. 3. 19. 12:21
option byte를 설정하고 알아서 reconnect 하는데 이때 리부팅이 되는것 같긴하다.
| ./STM32_Programmer_CLI -c port=SWD -ob DBANK=1 -d ~/STM32CubeIDE/stm32g473/stm32g476/Debug/stm32g476.elf -v -rst ------------------------------------------------------------------- STM32CubeProgrammer v2.21.0 ------------------------------------------------------------------- ST-LINK SN : 35FF72064D53373233492143 ST-LINK FW : V2J45S7 Board : -- Voltage : 3.25V SWD freq : 4000 KHz Connect mode: Normal Reset mode : Software reset Device ID : 0x469 Revision ID : Rev X Device name : STM32G47x/G48x/G414 Flash size : 256 KBytes Device type : MCU Device CPU : Cortex-M4 BL Version : 0xD5 Debug in Low Power mode enabled UPLOADING OPTION BYTES DATA ... Bank : 0x00 Address : 0x40022020 Size : 20 Bytes [==================================================] 100% Bank : 0x01 Address : 0x40022044 Size : 16 Bytes [==================================================] 100% Bank : 0x02 Address : 0x40022070 Size : 8 Bytes [==================================================] 100% PROGRAMMING OPTION BYTES AREA ... Bank : 0x00 Address : 0x40022020 Size : 20 Bytes [==================================================] 100% Reconnecting... Reconnected ! UPLOADING OPTION BYTES DATA ... Bank : 0x00 Address : 0x40022020 Size : 20 Bytes [==================================================] 100% Bank : 0x01 Address : 0x40022044 Size : 16 Bytes [==================================================] 100% Bank : 0x02 Address : 0x40022070 Size : 8 Bytes [==================================================] 100% OPTION BYTE PROGRAMMING VERIFICATION: Option Bytes successfully programmed Time elapsed during option Bytes configuration: 00:00:01.187 Opening and parsing file: stm32g476.elf Memory Programming ... File : stm32g476.elf Size : 18.32 KB Address : 0x08000000 Erasing memory corresponding to segment 0: Erasing internal memory sectors [0 9] Download in Progress: [==================================================] 100% File download complete Time elapsed during download operation: 00:00:00.589 Verifying... Read progress: [==================================================] 100% Time elapsed during verifying operation: 00:00:00.120 Download verified successfully MCU Reset Software reset is performed |
도움말
| $ ./STM32_Programmer_CLI ------------------------------------------------------------------- STM32CubeProgrammer v2.21.0 ------------------------------------------------------------------- Usage : STM32_Programmer_CLI.exe [command_1] [Arguments_1][[command_2] [Arguments_2]...] Generic commands: -?, -h, --help : Show this help -c, --connect : Establish connection to the device <port=<PortName> : Interface identifier. ex COM1, /dev/ttyS0, usb1, JTAG, SWD, JLINK...) USB port optional parameters: [sn=<serialNumber>] : Serial number of the usb dfu [PID=<Product ID>] : Product ID. ex: 0xA38F, etc, default 0xDF11 [VID=<Vendor ID>] : Vendor ID. ex: 0x0389, etc, default x0483 UART port optional parameters: [br=<baudrate>] : Baudrate. ex: 115200, 9600, etc, default 115200 [P=<parity>] : Parity bit, value in {NONE,ODD,EVEN}, default EVEN [db=<data_bits>] : Data bit, value in {6, 7, 8} ..., default 8 [sb=<stop_bits>] : Stop bit, value in {1, 1.5, 2} ..., default 1 [fc=<flowControl>] : Flow control Value in {OFF,Hardware,Software} ..., default OFF rts=<status> : low or high dtr=<status> : low or high Not supported for STM32MP [noinit=noinit_bit]: Set No Init bits, value in {0,1} ..., default 0 [console] : Enter UART console mode JTAG/SWD debug port optional parameters: [freq=<frequency>] : Frequency in KHz. Default frequencies: 4000 SWD 9000 JTAG with STLINKv2 8000 SWD 21333 with STLINKv3 [index=<index>] : Index of the debug probe. default index 0 [sn=<serialNumber>]: Serial Number of the debug probe [ap=<accessPort>] : Access Port index to connect to. default ap 0 [mode=<mode>] : Connection mode. Value in {UR/HOTPLUG/NORMAL/POWERDOWN/HWRSTPULSE} default mode: NORMAL [reset=<mode>] : Reset modes: SWrst/HWrst/Crst. Default mode: SWrst Reset mode with UR connection mode is HWrst [shared] : Enable shared mode allowing connection of two or more instances of STM32CubeProgrammer or other debugger to the same ST-LINK probe. [tcpport=<Port>] : Port used for running ST-Link Server, default 7184 [LPM] : Enable debug in Low Power mode(default mode) [dLPM] : Disable debug in Low Power mode [getAuthID] : Get device identification (Option only for STM32U5 series) [speed=<Reliable/fast>]: Choose flashing Reliable/fast (Option only for STM32U5 series) [TargetSel=<TargetSel>]: Specifies the target device by its Target Sel value SPI port optional parameters: [br=<baudrate>] : Baudrate. [cpha=<cpha_val>] : 1Edge or 2Edge. default 1Edge [cpol=<cpol_val>] : low or high [crc=<crc_val>] : enable or disable (0/1). [crcpol=<crc_pol>] : crc polynom value. [datasize=<size>] : 8bit/16bit [direction=<val>] : Direction: 2LFullDuplex/2LRxOnly/1LRx/1LTx [firstbit=<val>] : First Bit: MSB/LSB [frameformat=<val>]: Frame Format: Motorola/TI [mode=<val>] : Mode: master/slave [nss=<val>] : NSS: soft/hard [nsspulse=<val>] : NSS pulse: Pulse/NoPulse [delay=<val>] : Delay: Delay/NoDelay, delay of few microseconds [noinit=noinit_bit]: Set No Init bits, value in {0,1} ..., default 0 CAN port optional parameters: [br=<rbaudrate>] : Baudrate : 125, 250, 500, 1000 Kbps, default 125 [mode=<canmode>] : CAN Mode : NORMAL, LOOPBACK..., default NORMAL [ide=<type>] : CAN Type : STANDARD or EXTENDED, default STANDARD [rtr=<format>] : Frame Format: DATA or REMOTE, default DATA [fifo=<afifo>] : Msg Receive : FIFO0 or FIFO1, default FIFO0 [fm=<fmode] : Filter Mode : MASK or LIST, default MASK [fs=<fscale>] : Filter Scale: 16 or 32, default 32 [fe=<fenable>] : Filter Activation : ENABLE or DISABLE, default ENABLE [fbn=<fbanknb>] : Filter Bank Number : 0 to 13, default 0 [noinit=noinit_bit]: Set No Init bits, value in {0,1} ..., default 0 I2C port optional parameters: [add=<ownadd>] : Slave address : address in hex format [br=<sbaudrate>] : Baudrate : 100 or 400 Kbps, default 400 [sm=<smode>] : Speed Mode : STANDARD or FAST, default FAST [am=<addmode>] : Address Mode : 7 or 10 bits, default 7 [af=<afilter>] : Analog filter : ENABLE or DISABLE, default ENABLE [df=<dfilter>] : Digital filter : ENABLE or DISABLE, default DISABLE [dnf=<dnfilter>] : Digital noise filter : 0 to 15, default 0 [rt=<rtime>] : Rise time : 0-1000(STANDARD), 0-300(FAST), default 0 [ft=<ftime>] : Fall time : 0-300 (STANDARD), 0-300(FAST), default 0 [noinit=noinit_bit]: Set No Init bits, value in {0,1} ..., default 0 -version, --version : Displays the tool's version -l, --list : List all available communication interfaces <uart> : UART interface <usb> : USB interface <st-link> : st-link interface <stlink> <st-link-only> : Enumarte st-link list without connecting and intruse the target <stlink-only> Access port number is set to zero. <shared> : Allowing to list all boards connected to other instance(s) <stlink-shared> of STM32CubeProgrammer where the shared mode is enabled. -getTargetSelList : List all devices currently connected through SWD Multidrop -q, --quietMode : Enable quiet mode. No progress bar displayed -log, --log : Store the detailed output in log file [<file_Path.log>] : Path of the log file, default path = $HOME/.STM32Programmer/trace.log -vb, --verbosity : Specify verbosity level <Level> : Verbosity level, value in {1, 2, 3} -y, --yes : Ignore confirmation prompt message Available commands for STM32 MCU: --skipErase : Skip sector erase before programming -sl, --safelib : Add a segment into a firmware file (elf,bin hex,srec and s19) containing computed CRC values To use only with the safety lib component <file_path> : File path to be modified <start_address> : Flash memory start address <end_address> : Flash memory end address <slice_size> : Size of data per CRC value <pattern> : Optional pattern from 0x0 to 0xFF. Default pattern 0x00 -ms, --mergesbsfu : Add a binary header and a sbsfu segment to an elf file <elf_file_path> : File path to be modified <header_file_path> : Header file path <sbsfu_file_path> : SBSFU file path -e, --erase : Erase memory pages/sectors devices: Not supported for STM32MP [all] : Erase all sectors [<sectorsCodes>] : Erase the specified sectors identified by sectors codes. ex: 0, 1, 2 to erase sectors 0, 1 and 2 for EEPROM : ed1 & ed2 [<[start end]>] : Erase the specified sectors starting from start code to end code, ex: -e [5 10] -w, --write -d, --download : Download the content of a file into device memory <file_path> : File path name to be downloaded: (bin, hex, srec, s19 elf, stm32 or tsv file) [<address>] : Start address of download [incremental] : Optional, new write mechanism If the parameter [incremental] is not indicated, the tool will use the legacy write mechanism The new write mechanism programs only modified sectors to accelerate the flashing operation The legacy write mechanism programs the full firmware into flash memory -w32 : Write a 32-bits data into device memory <address> : Start address of download <32-bit_data> : 32-bit data to be downloaded values should be separated by space -w16 : Write a 16-bits data into device memory <address> : Start address of download <16-bit_data> : 16-bit data to be downloaded values should be separated by space -w8 : Write a 8-bits data into device memory <address> : Start address of download <8-bit_data> : 8-bit data to be downloaded values should be separated by space -v, --verify : Verify if the programming operation is achieved successfully [fast] : Optional, new verify mechanism If the parameter [fast] is not indicated, the tool will use the legacy verify mechanism The new verify mechanism verifies the integrity of data sector per sector The legacy verify mechanism verifies the integrity of data byte per byte -nv, --noverify : Do not verify if the programming operation is achieved successfully, used with -w32/-w16/-w8 commands -checksum, --checksum : Memory checksum calculation <address> : Optional, Start address <size> : Optional, Size of memory region : If the parameters <address> and <size> are not indicated, the tool will calculate the full internal Flash -r32 : Read a 32-bit data from device memory <address> : Read start address <size> : Size of data -r16 : Read a 16-bit data from device memory <address> : Read start address <size> : Size of data -r8 : Read a 8-bit data from device memory <address> : Read start address <size> : Size of data -rst : Reset system -hardRst : Hardware reset -rstbl : Reset Bootloader Available only with JTAG/SWD debug port -halt : Halt core -run : Run core -step : Step core Available only with JTAG/SWD debug port -score : Get core status Available only with JTAG/SWD debug port -coreReg : Read/Write core registers [<core_register>] R0/../R15/PC/LR/PSP/MSP/XPSR/APSR/IPSR/EPSR/ PRIMASK/BASEPRI/FAULTMASK/CONTROL [core_reg=<value>] value in case of write opration Note: multiple registers can be handled at once Available only with JTAG/SWD debug port -r, --read -u, --upload : Upload the device memory content to a .bin/.hex/.srec/.s19 file <address> : Start address of read and upload <size> : Size of memory content to be read <file_path> : file path with .bin/.hex/.srec/.s19 extension -el, --extload : Select a custom external memory-loader for JTAG/SWD <file_path> : External memory-loader file path -elbl, --extloadbl : Select a custom external memory-loader for Bootloader interface (SFIx only) <file_path> : External memory-loader file path -s, --start -g, --go : Run the code at the specified address. [<address>] : Start address -rdu, --readunprotect: Remove memory's Read Protection by shifting the RDP level from level 1 to level 0. -tzenreg, --tzenregression: Remove TrustZone Protection by disabling the TZEN from 1 to 0. -ob, --optionbytes : This command allows the user to manipulate the device 's OptionBytes by displaying or modifying them. [displ] : This option allows the user to display the whole set of Option Bytes. [unlockchip] : This option allows the user to unlock the chip in case of bad Option Bytes already programmed. [OptByte=<value>] : This option allows the user to program the given Option Byte. -force_no_da, --force_no_da : Froce OB programming if the DA is not already configured. Available only for STM32H50x devices -noreconnect, --noreconnect : Programming OB without performing a reconnect -w32dbgmcu : Write a 32-bits data into DBGMCU DBG AUTH HOST register <32-bit_data> 32-bit data to be downloaded, only for STM32H5xx devices. -lockRDP1, -setOEM1KEY : Lock RDP level 1 <LSB> : OEM1 least significant bytes key <MSB> : OEM1 most significant bytes key -unlockRDP1 : Unlock RDP level 1 <LSB> : OEM1 least significant bytes key <MSB> : OEM1 most significant bytes key -lockRDP2, -setOEM2KEY : Lock RDP level 2 <LSB> : OEM2 least significant bytes key <MSB> : OEM2 most significant bytes key -unlockRDP2 : Unlock RDP level 2 <LSB> : OEM2 least significant bytes key <MSB> : OEM2 most significant bytes key -ssigfoxc : Save the chip Certificate, supported for STM32WL devices <file_path> : Certificate file path -wsigfoxc : Write the Sigfox credential, supported for STM32WL devices <file_path> : Certificate file path (binary, header) <address> : start address for write -fillmemory : Fill memory with the given pattern from the chosen address. <start_address> : Start address for write. The address 0x08000000 is used by default [size=<value>] : Size of the data to write [pattern=<value>] : The pattern value to write. [dataWidth=8|16|32]: The filling data size: 8 bits is selected by default. -blankcheck : Verifies that the STM32 Flash memory is blank. If the Flash memory is not blank, the first address with data is highlighted in a message. -fchecksum, --file-checksum : File checksum calculation <file_path> : File path Beta commands: -regdump : Read and dump Core and MCU registers <file_path> : Log file path with extension .log or .txt [choice=<number>] : Device number from the list of compatible devices (optional), this list is displayed if the command is performed without this optional argument -hf : Hard fault analyzer Helps to identify system faults that occur when the CPU is driven into a fault condition by the application code. -pwr, --power : Perform power ON/OFF, only for STLINK supporting this capability <on/off> : Select the power type [index=<number>] : Index of the debug probe. -r32fast : Read a 32-bit data from device memory with direct access Only for accessible internal memories via ST-LINK interfaces <address> : Read start address <size> : Size of data Available commands for STM32 MPU: -c, --connect : Establish connection to the device <port=<PortName> : Interface identifer. ex COM1, /dev/ttyS0, usb1) USB port optional parameters: [sn=<serialNum>] : Serial number of the usb dfu [serial] : Activate USB serial Gadget for MPU devices UART port optional parameters: [br=<baudrate>] : Baudrate. ex: 115200, 9600, etc, default 115200 [P=<parity>] : Parity bit, value in {NONE,ODD,EVEN}, default NONE [db=<data_bits>] : Data bit, value in {6, 7, 8} ..., default 8 [sb=<stop_bits>] : Stop bit, value in {1, 1.5, 2} ..., default 1 [fc=<flowControl>] : Flow control (Not yet supported for STM32MP) Value in {OFF,Hardware,Software} ..., default OFF [noinit=noinit_bit]: Set No Init bits, value in {0,1} ..., default 0 -s, --start -g, --go : Run the code at the specified partition ID. [<partitionID>] : Partition ID If not specified, last loaded partition will be started [<startAdress>] : Start address If not specified, last loaded segment address [<noack>] : No acknowledgment required If not specified, acknowledgment will be required -detach : Send detach command to DFU -wb : Write blob <blob_file_path> : Blob file path -pmic : Program PMIC NVM <PMIC file_path> : PMIC file_path -gc, --getcertificate : Get the chip Certificate, supported for devices with security features <file_path> : Certificate file path into which the chip certificate will be uploaded <tfa-ssp-path> : Input TFA SSP signed firmware path. Used only with STM32MP1 devices -p, --phaseID : Display the current partition ID to be loaded -w, --write -d, --download : Download the content of a file into device memory <file_path> : File path name to be downloaded: (bin, stm32 file <partition_id> : Partition ID to be downloaded -rp, --readPart : Upload a memory partion ID content to a .bin file <partionID> : Partion to be read [<offset address>] : Offset address of read and upload <size> : Size of partion content to be read <file_path> : Binary file path -ssp, --ssp : Program an SSP file <ssp_file_path> : SSP file path to be programmed, bin or ssp extension <ssp-fw-path> : SSP signed firmware path [hsm=0|1] : Set user option for HSM use value in {0 (do not use HSM), 1 (use HSM)} Default value : hsm=0 <lic_path|slot=slotID> : Path to the license file (if hsm=0) or reader slot ID if HSM is used (hsm=1) plugin=<plugin-fw-path> : Optional, binary plugin firmware path. Used only with STM32MP2x devices -tm : Force timeout <value> : Number of milliseconds -rst : Reset USB device OTP commands : -otp displ : This command allows the user to display all or parts of the OTP structure [word=<id>] : {Optional} display a specific OTP registers {values and status} Up to 96 OTP words [0 to 95], id value in hex/dec format -otp write : This command allows to fuse or update OTP words Up to 96 OTP words [0 to 95] at the same command line [lock] : {Optional} indicate the operation type, update or permanent lock [word=<id>] : This field contains the OTP word number in hex/dec format [value=<value>] : Value to be written in hex format -otp lock : This command allows to fuse permanently OTP words Up to 96 OTP words [0 to 95] at the same command line [word=<id>] : This field contains the OTP word number in hex/dec format -otp fwrite : This command allows to program a binary file [lock] : {Optional} indicate the operation type, update or permanent lock <bin_path> : Binary file path, 32-bits aligned data [word=<id>] : OTP word number in hex/dec format, start word of program STM32WB0 series OTP store command: -storekeyotp , --storekeyotp : Store OTP key <key_path.c> : Folder with the public_key.c file to store in OTP <start_address> : Start FW address MCU Secure programming specific commands: -installipmodule, --installipmodule : Install ip module file <file_path> : Path of smu file to be programmed [hsm=0|1] : Set user option for HSM use value in {0 (do not use HSM), 1 (use HSM)} Default value : hsm=0 <lic_path|slot=slotID> : Path to the license file (if hsm=0) or reader slot ID if HSM is used (hsm=1) note that if it is the case of global license, please use hsm = 0 with license path. [<address>] : Destination address of the smu module -updateipmodule, --updateipmodule : update ip module. <file_path> : Path of SMU file containing the update. [<address>] : Destination address of the smu module -sfi, --sfi : Program an sfi file [<protocol=Ptype>] : Protocol type to be used : static/live Only static protocol is supported so far Default value static <file_path> : Path of sfi file to be programmed [hsm=0|1] : Set user option for HSM use value in {0 (do not use HSM), 1 (use HSM)} Default value : hsm=0 <lic_path|slot=slotID> : Path to the SFI license file (if hsm=0) or reader slot ID if HSM is used (hsm=1) -ssfi, --ssfi : Program an ssfi file <ssfi_file_path> : Path of ssfi file to be programmed <rsse_file_path> : RSSe file path -rsse, --rsse : Set the RSSe file path, supported for devices with security extension <file_path> : RSSe file path -mcsv, --mcsv : Set the MCSV file path indicating SFI's modules configuration supported for STM32H5xx devices <file_path> : MCSV file path with .mcsv extension -ecsv, --ecsv : Set the ECSV file path indicating SFI's external modules configuration supported for STM32H5xx devices <file_path> : ECSV file path with .ecsv extension -a, --abort : This command allows the user to clean a not properly finished process. The currently ongoing operation will stop and the system will return to idle state -dsecurity : Disable the security for STM32WL -setdefaultob : Set default Option Bytes for STM32WL -rssgetversion, --rssgetversion : get the version of RSS HSM related commands: -hsmgetinfo : Read the HSM available information [slot=<SlotID>] : Slot ID of the Smart Card Reader Default value: slot=1 (the PC integrated SC reader) -hsmgetcounter : Read the current value of the license counter [slot=<SlotID>] : Slot ID of the Smart Card Reader Default value: slot=1 (the PC integrated SC reader) -hsmgetfwid : Read the Firmware/Module Identifier [slot=<SlotID>] : Slot ID of the Smart Card Reader Default value: slot=1 (the PC integrated SC reader) -hsmgetstatus : Read the current card life-cycle state [slot=<SlotID>] : Slot ID of the Smart Card Reader Default value: slot=1 (the PC integrated SC reader) -hsmgetlicense : Get a license for the current chip if counter is not null <file_path> : File path into which the received license will be stored [slot=<SlotID>] : Slot ID of the Smart Card Reader Default value: slot=1 (the PC integrated SC reader) [protocol=<Ptype>] : Protocol type to be used : static/live Only static protocol is supported so far Default value static <tfa-ssp-path> : Input TFA SSP signed firmware path. Used only for STM32MP1 devices -hsmgetlicensefromcertifbin, -hsmglfcb : Get a license for the input certificate if counter is not null <certif_file_path.bin> : Input certificate file path <license_file_path.bin> : File path into which the received license will be stored [slot=<SlotID>] : Slot ID of the Smart Card Reader Default value: slot=1 (the PC integrated SC reader) [protocol=<Ptype>] : Protocol type to be used : static/live Only static protocol is supported so far Default value static STM32WBxx specific commands: -getuid64 : Read the device UID -fusgetstate : Read the FUS state -fusopgetversion : Read the FUS Operator version -antirollback : Perform the antirollback operation (Only on Bootloader interface) -startfus : Perform the startfus operation Firmware Upgrade commands: -fwdelete : Delete the BLE stack firmware -fwupgrade : Upgrade the BLE stack firmware or the FUS firmware <file_path> : New firmware image file path <address> : Start address of download [firstinstall=0|1] : 1 if it is a first install otherwise 0 optional, Default value: firstinstall=0 [startstack=0|1] : 1 to start the stack after the upgrade otherwise 0 optional, Default value: startstack=1 -v : Verify if the download operation is achieved successfully before starting upgrade -startwirelessstack : Start the wireless stack Key management commands: -authkeyupdate : Authentication key update <file_path> : New authentication key file path. : This is the public key generated by : STM32TrustedPackageCreator using -sign command. -authkeylock : Authentication key lock : Once locked, it's no longuer possible to change it : using authkeyupdate command -wusrkey : Write user key <file_path> : User key file path <keytype=1|2|3> : User key type, values : 1, 2 or 3. : 1 = simple key, 2 = master key, 3 = encrypted key. Serial Wire Viewer specific commands: -swv : Printf via SWO <freq=<frequency>> : System Clock in MHz <portnumber=0-31|all> : ITM port number, values : 0-31, or all for All ports [<file_Path.log>] : Path of the SWV log file (optional), : default path = $USER_HOME/STMicroelectronics/STM32Programmer/SWV_Log/swv.log -RA : Start the reception of swv automatically -startswv : Printf via SWO & Start the reception of swv automatically Script Manager command: -script : Start the execution of Script File <file_Path.prg> : Path of the script file (.prg) Provisionning Command: -sdp : Start the OBKey Provisioning <File_Path> : OBKey File Path Provisioning with password : -pwd : Start Provisioning with password value=<password_value> : Password value path=<password_path> : location of password file to be used in Debug Authentication Set Product State RSS Command: -psrss : Start the RSS Product State <Value> : An hexadecimal value Get Product State RSS Command: -psrss displ : Start the Get RSS Product State Option Bytes RSS Command: -obrss : Start the Option Bytes RSS Change <Value 1> <Value 2> <Value 3> <Value 4> : An hexadecimal values Debug Authentication options: [debugauth=<1|2>] : to choose starting authentication(1) or discovery(2) [pwd=<password_file_path>] : required in case of authentication with password [key=<key_file_path>] : required in case of authentication with certificate [cert=<certificate_file_path>] : required in case of authentication with certificate [per=<requested_permission>] : required in case of authentication with certificate. : Each permission is referred to by a specific letter and a numerical bit value. : Enable debugauth=2 to access the permissions list with bit numbers and letters. : Debug Authentication requires the selection of one specific permission. : Certain products also provide optional actions to choose from. Example:Forced Download Key Wrapping Command -rssekw : Set The Key Wrapping RSSe File Path supported for devices with security extension <file_path> : RSSe Key Wrapping file path <file_path> : Private Key .pem file path [Not to be added for ECC CPVK wrapping using DHUK or DHUK xOR BHK] <file_path> : Output .bin file path [KeyType=<eccchipfu|eccchiplu>] : The Type of the ECC Chip Key to wrap [ExportPublicKey=<Yes|No>] : Generate or Not the public Key [WrappingKeySelect=<DHUK|DHUK_XOR_BHK>] : Used Method to wrap the private key [KeyUsage=<ECDSA_USAGE_SIGN|ECC_USAGE_SCALAR_MUL>] : Usage of the private key [SecAttr=<SECURE|NON_SECURE>] : Secure or Non Secure context [PrivAttr=<PRIVILEGE|NON_PRIVILEGE>] : Privileged or Non Priviledged context [AESMode=<ECB|CBC|GCM>] : AES mode for wrapping with user Key |
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embeded/jetson2026. 3. 19. 12:13
jetson nano 캐리어와 다르게 12V 를 넣어주어야 켜지는데
A02 를 꽂았는데 아무반응이 없는 느낌.. 전용 펌웨어 넣어주어야 하나..
Seeed BSP가 nano용으로 있긴한데
상단에 보면 Jetson nano 4GB 라서 B01 용 모듈을 지원할 것 같은 느낌인데...
[링크 : https://wiki.seeedstudio.com/reComputer_J2021_J202_Flash_Jetpack/]
[링크 : https://www.seeedstudio.com/reComputer-J202-Carrier-Board-for-Jetson-Xavier-NX-p-5397.html]
[링크 : https://files.seeedstudio.com/wiki/J202/reComputer_Jetson-J202_datasheet.pdf]
+
B01 2GB 삽입하고
12V / USB-C / FC REC-GND 연결하니 jetson nano로 인식된다.
그럼 진행하면 되긴하는데.. 이거 sd 카드로 구울수 있는건 맞나?
| |__ Port 1: Dev 16, If 0, Class=Vendor Specific Class, Driver=, 480M ID 0955:7f21 NVIDIA Corp. |
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