구차니의 잡동사니 모음

The different modes that Advanced Timing allows end users to select are:

• Electronic Industries Alliance (EIA-861B) refers to a CEA/EIA standard which consists of display timing and formats supported by Digital Televisions
• Generalized Timing Formula (GTF) is a method of generating industry standard timings used by a wide variety of display products
• Display Monitor Timings (DMT) are a list of VESA standard pre-defined timings which are commonly used within the Computer industry.
• Coordinated Video Timings (CVT) were released on March 2003 as the newest VESA standard for generating display timings
• Coordinated Video Timings-Reduced Blanking (CVT-RB) is geared specifically for non-CRT display devices. CVT-RB offers reduced horizontal and vertical blanking periods and allows a lower pixel clock rate and higher frame rates.
• EDID Timing is the preferred timing standard defined by the display's Extended Display Identification Data (EDID) value. EDID is a standard data structure that defines the display device's configuration data and mode support which allows optimum use of the display 

The standard was adopted in 2002 and superseded the Generalized Timing Formula. 

 타이밍 모드

 표준

 CEA/EIA-861B

 ???

 GTF 

 1999

 DMT

 2007 (Version 1.0 Rev 0.11)

 CVT 

 2002 (Version 1.0 Rev 0.9)

 CVT-RB

 2007 (Version 1.0 Rev 0.11)

 EDID 

 1996 (Version 1.0 Rev 0.4)

he standard was adopted in 1999, and was superseded by the Coordinated Video Timings specification in 2002. 

vga640x480 vga(

CLOCK_50,

KEY[0],

LED,

GP0[6],

GP0[5],

{GP0[16],GP0[19],GP0[18],GP0[21]},

{GP0[12],GP0[15],GP0[14],GP0[17]},

{GP0[8],GP0[9],GP0[10],GP0[13]}

); 

module vga640x480(

input clk,

input rst,

output [7:0] LED,

output reg hsync,

output reg vsync,

output [3:0] r,

output [3:0] g,

output [3:0] b

);

reg clk25;

reg [9:0] horizontal_counter;

reg [9:0] vertical_counter;

reg [9:0] X;

reg [9:0] Y;

wire [7:0] red;

wire [7:0] green;

wire [7:0] blue;

assign r[3:0] = ((horizontal_counter >= 144) 

&& (horizontal_counter < 784) 

&& (vertical_counter >=39)

&& (vertical_counter < 519)) ? red : 4'b000; 

assign g[3:0] = ((horizontal_counter >= 144) 

&& (horizontal_counter < 784) 

&& (vertical_counter >=39)

&& (vertical_counter < 519)) ? green : 4'b000; 

assign b[3:0] = ((horizontal_counter >= 144) 

&& (horizontal_counter < 784) 

&& (vertical_counter >=39)

&& (vertical_counter < 519)) ? blue : 4'b000; 

assign red =   ((horizontal_counter >= 144)&&(horizontal_counter < 344) ) ? 4'b1111 : 4'b0000;

assign green = ((horizontal_counter >= 344)&&(horizontal_counter < 544) ) ? 4'b1111 : 4'b0000;

assign blue =  ((horizontal_counter >= 544)&&(horizontal_counter < 784) ) ? 4'b1111 : 4'b0000;

always @(posedge clk)

begin

if (clk25 == 0)

begin

   clk25 <= 1;

end   

else

begin

clk25 <= 0;

   end

end

always @(posedge clk25)

begin

if ((horizontal_counter > 0) && (horizontal_counter < 97))// -- 96+1

begin

hsync <= 0;

end

else

begin

hsync <= 1;

end 

if ((vertical_counter > 0 ) && (vertical_counter < 3 )) //-- 2+1

begin

vsync <= 0;

end

else

begin

vsync <= 1;

end

horizontal_counter <= horizontal_counter+1;

if (horizontal_counter == 800) 

begin

vertical_counter <= vertical_counter+1;

horizontal_counter <= 0;

end

if (vertical_counter == 521)

begin

vertical_counter <= 0;

end

end

endmodule  

vga640x480 vga(

CLOCK_50,

KEY[0],

LED,

GP0[6],

GP0[5],

{GP0[16],GP0[19],GP0[18],GP0[21]},

{GP0[12],GP0[15],GP0[14],GP0[17]},

{GP0[8],GP0[9],GP0[10],GP0[13]}

); 

module vga640x480(

input clk,

input rst,

output [7:0] LED,

output hsync,

output vsync,

output [3:0] r,

output [3:0] g,

output [3:0] b

);

parameter HSYNC = 189;

parameter HBP = (HSYNC + 95);

parameter HVID = (HBP + 1260);

parameter HFP = (HVID + 47);

parameter VSYNC = 3000;

parameter VBP = (VSYNC + 51000);

parameter VVID = (VBP + 762500);

parameter VFP = (VVID + 17500);

reg [19:0] cnt;

always @ (posedge clk or negedge rst)

begin

if (!rst)

begin

cnt <= 0;

end

else

begin

cnt <= cnt + 1;

if(cnt > 834000)

cnt <= 0;

end

end

assign hsync = ((cnt % 1590) < 189) ? 0 : 1;

assign vsync = (cnt < 3000) ? 0 : 1;

assign r = ((hsync & vsync) == 1 ? 4'b1111 : 4'b0000);

assign g = ((hsync & vsync) == 1 ? 4'b1111 : 4'b0000);

assign b = ((hsync & vsync) == 1 ? 4'b1111 : 4'b0000);

assign LED[0] = ~vsync;

assign LED[1] = ~hsync;

endmodule 

module vga800x600x60(

input clk,

input rst,

output [7:0] LED,

output hsync,

output vsync,

output [3:0] r,

output [3:0] g,

output [3:0] b

);

parameter HSYNC = 160;

parameter HBP = (HSYNC + 95);

parameter HVID = (HBP + 1260);

parameter HFP = (HVID + 47);

parameter VSYNC = 5300;

parameter VBP = (VSYNC + 51000);

parameter VVID = (VBP + 762500);

parameter VFP = (VVID + 17500);

reg [19:0] cnt;

always @ (posedge clk or negedge rst)

begin

if (!rst)

begin

cnt <= 0;

end

else

begin

cnt <= cnt + 1;

if(cnt > 828950)

cnt <= 0;

end

end

assign hsync = ((cnt % 1320) < 160) ? 0 : 1;

assign vsync = (cnt < 5300) ? 0 : 1;

assign r = ((hsync & vsync) == 1 ? 4'b1111 : 4'b0000);

assign g = ((hsync & vsync) == 1 ? 4'b1111 : 4'b0000);

assign b = ((hsync & vsync) == 1 ? 4'b1111 : 4'b0000);

assign LED[0] = ~vsync;

assign LED[1] = ~hsync;

endmodule  

For VESA 800*600 @ 60Hz: 

Fh (kHz) :37.88 

A (us) :26.4 

B (us) :3.2 

C (us) :2.2 

D (us) :20.0 

E (us) :1.0 

Fv (Hz) :60.32 

O (ms) :16.579 

P (ms) :0.106 

Q (ms) :0.607 

R (ms) :15.84 

S (ms) :0.026 

vga640x480 vga(

CLOCK_50,

KEY[0],

LED,

GP0[6],

GP0[5],

{GP0[16],GP0[19],GP0[18],GP0[21]},

{GP0[12],GP0[15],GP0[14],GP0[17]},

{GP0[8],GP0[9],GP0[10],GP0[13]}

); 

module vga640x480(

input clk,

input rst,

output [7:0] LED,

output reg hsync,

output reg vsync,

output [3:0] r,

output [3:0] g,

output [3:0] b

);

reg clk25;

reg [9:0] horizontal_counter;

reg [9:0] vertical_counter;

reg [9:0] X;

reg [9:0] Y;

wire [7:0] red;

wire [7:0] green;

wire [7:0] blue;

assign r[3:0] = ((horizontal_counter >= 144) 

&& (horizontal_counter < 784) 

&& (vertical_counter >=39)

&& (vertical_counter < 519)) ? 4'b1111 : 4'b000; 

assign g[1:0] = ((horizontal_counter >= 144) 

&& (horizontal_counter < 784) 

&& (vertical_counter >=39)

&& (vertical_counter < 519)) ? 4'b1111 : 4'b000; 

assign b[2:0] = ((horizontal_counter >= 144) 

&& (horizontal_counter < 784) 

&& (vertical_counter >=39)

&& (vertical_counter < 519)) ? 4'b1111 : 4'b000; 

assign red =   ((horizontal_counter >= 144)&&(horizontal_counter < 344) ) ? 4'b1111 : 4'b0000;

assign green = ((horizontal_counter >= 344)&&(horizontal_counter < 544) ) ? 4'b1111 : 4'b0000;

assign blue =  ((horizontal_counter >= 544)&&(horizontal_counter < 784) ) ? 4'b1111 : 4'b0000;

always @(posedge clk)

begin

if (clk25 == 0)

begin

   clk25 <= 1;

end   

else

begin

clk25 <= 0;

   end

end

always @(posedge clk25)

begin

if ((horizontal_counter > 0) && (horizontal_counter < 97))// -- 96+1

begin

hsync <= 0;

end

else

begin

hsync <= 1;

end 

if ((vertical_counter > 0 ) && (vertical_counter < 3 )) //-- 2+1

begin

vsync <= 0;

end

else

begin

vsync <= 1;

end

horizontal_counter <= horizontal_counter+1;

if (horizontal_counter == 800) 

begin

vertical_counter <= vertical_counter+1;

horizontal_counter <= 0;

end

if (vertical_counter == 521)

begin

vertical_counter <= 0;

end

end

endmodule