Halt all cores 를 체크해서
Cortex-M7을 멈추면 Cortex-M4 도 같이 멈추고
Cortex-M4 에는 Halt 옵션이 없으니 M7을 멈출수 없어서 M4만 멈췄나 보다.
| stm32cubeide(eclipse) project clean시 빌드 하지 않기 (0) | 2024.07.24 |
|---|---|
| 우분투에서 stm32cubeide 삭제 (0) | 2024.07.24 |
| STM32H750 operation mode (0) | 2024.07.22 |
| STM32 MPU(Memory Protection Unit) (2) | 2024.07.22 |
| STM32 HSEM (Hardware SEMaphore) (0) | 2024.07.22 |
소스를 뒤져보면서 메뉴얼 찾아보는 중
stm32h7xx_hal_pwr_ex.c 파일에 보면 D3Domain 이라고 PWR_CPUCR_RUN_D3 라고
d3 도메인의 cpu (cortex-m4)를 살리는 녀석으로 보인다.
| void HAL_PWREx_ConfigD3Domain (uint32_t D3State) { /* Check the parameter */ assert_param (IS_D3_STATE (D3State)); /* Keep D3/SRD in run mode */ MODIFY_REG (PWR->CPUCR, PWR_CPUCR_RUN_D3, D3State); } |
| /******************** Bit definition for PWR_CPUCR register *****************/ #define PWR_CPUCR_RUN_D3_Pos (11U) #define PWR_CPUCR_RUN_D3_Msk (0x1UL << PWR_CPUCR_RUN_D3_Pos) /*!< 0x00000800 */ #define PWR_CPUCR_RUN_D3 PWR_CPUCR_RUN_D3_Msk /*!< Keep system D3 domain in RUN mode regardless of the CPU sub-systems modes */ /******************** Bit definition for PWR_CPU2CR register ****************/ #define PWR_CPU2CR_RUN_D3_Pos (11U) #define PWR_CPU2CR_RUN_D3_Msk (0x1UL << PWR_CPU2CR_RUN_D3_Pos) /*!< 0x00000800 */ #define PWR_CPU2CR_RUN_D3 PWR_CPU2CR_RUN_D3_Msk /*!< Keep system D3 domain in RUN mode regardless of the CPU sub-systems modes */ |
stm32h757xi.pdf 데이터 시트 31page
어.. D2 domain에 Cortex-M4 였네..
rm0399-stm32h745755-and-stm32h747757-advanced-armbased-32bit-mcus-stmicroelectronics.pdf
| 7.6.1 Operating modes Several system operating modes are available to tune the system according to the performance required, i.e. when the CPU(s) do not need to execute code and are waiting for an external event. It is up to the user to select the operating mode that gives the best compromise between low power consumption, short startup time and available wakeup sources. The operating modes allow controlling the clock distribution to the different system blocks and powering them. The system operating mode is driven by CPU1 subsystem, CPU2 subsystem and system D3 autonomous wakeup. A CPU subsystem can include multiple domains depending on its peripheral allocation (see Section 9.5.11: Peripheral clock gating control). The following operating modes are available for the different system blocks (see Table 34): • CPU subsystem modes: – CRun CPU and CPU subsystem peripheral allocated via RCC PERxEN bits are clocked. – CSleep: The CPU clocks is stalled and the CPU subsystem allocated peripheral(s) clock operate according to RCC PERxLPEN. – CStop: CPU and CPU subsystem peripheral clocks are stalled. • D1 domain and D2 domain modes: – DRun The domain bus matrix is clocked: - The domain CPU subsystem(a) is in CRun or CSleep mode, or - the other domain CPU subsystem(a) having an allocated peripheral in the domain is in CRun or CSleep mode. – DStop The domain bus matrix clock is stalled: - The domain CPU subsystem is in CStop mode and - The other domain CPU subsystem has no peripheral allocated in the domain. or the other domain CPU subsystem having an allocated peripheral in the domain is also in CStop mode and - At least one PDDS_Dn(b) bit for the domain select DStop. – DStandby The domain is powered down: - The domain CPU subsystem is in CStop mode and - The other domain CPU subsystem has no peripheral allocated in the domain or the other domain CPU subsystem having an allocated peripheral in the domain is also in CStop mode and - All PDDS_Dn(b) bits for the domain select DStandby mode. • System /D3 domain modes – Run/Run* The system clock and D3 domain bus matrix clock are running: - A CPU subsystem is in CRun or CSleep mode or - A wakeup signal is active. (i.e. System D3 autonomous mode) The Run* mode is entered after a POR reset and a wakeup from Standby. In Run* mode, the performance is limited and the system supply configuration shall be programmed in PWR control register 3 (PWR_CR3). The system enters Run mode only when the ACTVOSRDY bit in PWR control status register 1 (PWR_CSR1) is set to 1. – Stop The system clock and D3 domain bus matrix clock is stalled: - both CPU subsystems are in CStop mode. and - all wakeup signals are inactive. and - At least one PDDS_Dn(b) bit for any domain select Stop mode. – Standby The system is powered down: - both CPU subsystems are in CStop mode and - all wakeup signals are inactive. and - All PDDS_Dn(b) bits for all domains select Standby mode. In Run mode, power consumption can be reduced by one of the following means: •Lowering the system performance by slowing down the system clocks and reducing the VCORE supply level through VOS voltage scaling bits. •Gating the clocks to the APBx and AHBx peripherals when they are not used, through PERxEN bits. a. The domain CPU subsystem, for example CPU1 subsystem for D1 domain. a. The other domain CPU subsystem, for example CPU1 subsystem for D2 domain. |
| 9 Reset and Clock Control (RCC) The RCC block manages the clock and reset generation for the whole microcontroller, which embeds two CPUs: an Arm® Cortex®-M7 and an Arm® Cortex®-M4, called CPU1 and CPU2, respectively. The RCC block is located in the D3 domain (refer to Section 7: Power control (PWR) for a detailed description). The operating modes this section refers to are defined in Section 7.6.1: Operating modes of the PWR block. |
cpu1 power 용
cpu2 power 용. 서로 접근하면 되나?
| 우분투에서 stm32cubeide 삭제 (0) | 2024.07.24 |
|---|---|
| STM32H7 디버깅 설정(cubeIDE) (0) | 2024.07.22 |
| STM32 MPU(Memory Protection Unit) (2) | 2024.07.22 |
| STM32 HSEM (Hardware SEMaphore) (0) | 2024.07.22 |
| STM32H757 User configuration (0) | 2024.07.22 |
MMU 처럼 메모리 관리하는건 아니고, 메모리 접근을 관리하는 녀석인듯.
| This application note describes how to manage the memory protection unit (MPU) in the STM32 products The MPU is an optional component for the memory protection. Including the MPU in the STM32 microcontrollers (MCUs) makes them more robust and reliable. The MPU must be programmed and enabled before using it. If the MPU is not enabled, there is no change in the memory system behavior. This application note concerns all the STM32 products listed in Table 1 that include the Cortex®-M0+/M3/M4 and M7 design that supports the MPU. For more details about the MPU, refer to the following documents available on http://www.st.com • Programming manual STM32F7 series and STM32H7 series Cortex®-M7 processor (PM0253) • Programming manual STM32F10xxx/20xxx/21xxx/L1xxxx Cortex®-M3 (PM0056) • Programming manual STM32 Cortex®-M0+ MCUs programming manual (PM0223) • Programming manual STM32 Cortex®-M4 MCUs and MPUs (PM0214) • Programming manual STM32 Cortex®-M33 MCUs (PM0264) Table 1. Applicable products Type Product series Microcontrollers • STM32C0 series • STM32F1 series, STM32F2 series, STM32F3 series, STM32F4 series, STM32F7 series • STM32G0 series, STM32G4 series • STM32H5 series, STM32H7 series • STM32L0 series, STM32L1 series, STM32L4 series, STM32L4+ series, STM32L5 series • STM32U0 series, STM32U5 series • STM32WB series, STM32WB0 series |
MPU는 2개 있고, 각각의 CPU에 대해서 메모리 접근을 확인한다고.
꽤 중요한 녀석인데 데이터시트에 고작 아래의 내용이 전부냐?!
| 3.2 Memory protection unit (MPU) The devices feature two memory protection units. Each MPU manages the CPU access rights and the attributes of the system resources. It has to be programmed and enabled before use. Its main purposes are to prevent an untrusted user program to accidentally corrupt data used by the OS and/or by a privileged task, but also to protect data processes or read-protect memory regions. The MPU defines access rules for privileged accesses and user program accesses. It allows defining up to 16 protected regions that can in turn be divided into up to 8 independent subregions, where region address, size, and attributes can be configured. The protection area ranges from 32 bytes to 4 Gbytes of addressable memory. When an unauthorized access is performed, a memory management exception is generated. |
[링크 : https://www.st.com/resource/en/datasheet/stm32h757ai.pdf]
| STM32H7 디버깅 설정(cubeIDE) (0) | 2024.07.22 |
|---|---|
| STM32H750 operation mode (0) | 2024.07.22 |
| STM32 HSEM (Hardware SEMaphore) (0) | 2024.07.22 |
| STM32H757 User configuration (0) | 2024.07.22 |
| STM32CubeProgrammer (0) | 2024.07.22 |
multi CPU를 위한 하드웨어 세마포어 인듯.
그러니까.. 싱글 코어이거나, 이기종 CPU가 아니라면 달려있는 이유가 없는 모듈
[링크 : https://www.st.com/resource/en/product_training/STM32WB-System-Hardware-Semaphore-HSEM.pdf]
| STM32H750 operation mode (0) | 2024.07.22 |
|---|---|
| STM32 MPU(Memory Protection Unit) (2) | 2024.07.22 |
| STM32H757 User configuration (0) | 2024.07.22 |
| STM32CubeProgrammer (0) | 2024.07.22 |
| stm32h757xi / stm32h757i-eval (0) | 2024.07.19 |
이전에 메뉴얼 뒤지다 발견한 BCM7/BCM4는 어디서 접근이 가능한지, 설정이 가능한지 찾질 못했는데
프로그램 하나 설치하니 해피하게 해결.. -_-
왼쪽 세번째 아이콘 OB가 Option Bytes 인데
거기서 User Configuration 항목에 BCM4 / BCM7을 발견할 수 있다.
[링크 : https://blog.naver.com/chandong83/221652968153]
[링크 : https://www.st.com/en/development-tools/stm32cubeprog.html]
[링크 : https://blog.naver.com/chcbaram/221597488638]
+
| HAL_FLASH_Unlock(); HAL_FLASH_OB_Unlock(); HAL_FLASHEx_OBGetConfig(&OBInit); OBInit.OptionType = OPTIONBYTE_CM7_BOOTADD; OBInit.BootAddr0 = 0x08010000; OBInit.BootConfig = OB_BOOT_ADD0; HAL_FLASHEx_OBProgram(&OBInit); HAL_FLASH_OB_Launch() |
[링크 : https://community.st.com/t5/stm32-mcus-products/stm32h745-set-cm7-boot-addr0-from-cm4/td-p/654791]
+
| void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) { pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_BOR; /*Get WRP*/ pOBInit->WRPSector = FLASH_OB_GetWRP(); /*Get RDP Level*/ pOBInit->RDPLevel = FLASH_OB_GetRDP(); /*Get USER*/ pOBInit->USERConfig = FLASH_OB_GetUser(); /*Get BOR Level*/ pOBInit->BORLevel = FLASH_OB_GetBOR(); } |
| typedef struct { uint32_t OptionType; /*!< Option byte to be configured. This parameter can be a value of @ref FLASHEx_Option_Type */ uint32_t WRPState; /*!< Write protection activation or deactivation. This parameter can be a value of @ref FLASHEx_WRP_State */ uint32_t WRPSector; /*!< Specifies the sector(s) to be write protected. The value of this parameter depend on device used within the same series */ uint32_t Banks; /*!< Select banks for WRP activation/deactivation of all sectors. This parameter must be a value of @ref FLASHEx_Banks */ uint32_t RDPLevel; /*!< Set the read protection level. This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */ uint32_t BORLevel; /*!< Set the BOR Level. This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */ uint8_t USERConfig; /*!< Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. */ } FLASH_OBProgramInitTypeDef; |
| STM32 MPU(Memory Protection Unit) (2) | 2024.07.22 |
|---|---|
| STM32 HSEM (Hardware SEMaphore) (0) | 2024.07.22 |
| STM32CubeProgrammer (0) | 2024.07.22 |
| stm32h757xi / stm32h757i-eval (0) | 2024.07.19 |
| FT5336 - 정전식 터치 i2c (0) | 2021.07.06 |
별도의 독립 프로그램이다... -_-
리눅스 버전 받으면 zip으로 받아지고, 압축풀면 아래와 같이 exe와 linux 파일이 생기는데
linux는 900kb 정도로 용량이 작아서 쉘 스크립트 치곤 크네.. 하고 봤더니 ELF 실행파일.
그냥 ./SetupSTM32CubeProgrammer-2.17.0.linux 로 실행하면 된다.
| $ file * SetupSTM32CubeProgrammer-2.17.0.exe: PE32 executable (GUI) Intel 80386 (stripped to external PDB), for MS Windows SetupSTM32CubeProgrammer-2.17.0.linux: ELF 64-bit LSB executable, x86-64, version 1 (GNU/Linux), statically linked, for GNU/Linux 3.2.0, BuildID[sha1]=bcc7be207b463b7b004b10f7078d9d2be84d3902, with debug_info, not stripped jre: directory |
UI 색상 왜이래.. 다크모드라 그런가?
[링크 : https://www.st.com/en/development-tools/stm32cubeprog.html]
[링크 : https://blog.naver.com/chcbaram/221597488638]
귀찮아서 기본값으로 설치했는데.. 프로그램 등록이 되지 않아 수동으로 실행해야 한다.
GUI는 아래의 명령어로 실행하면 된다.
| ~/STMicroelectronics/STM32Cube/STM32CubeProgrammer/bin$ ./STM32CubeProgrammer |
| STM32 HSEM (Hardware SEMaphore) (0) | 2024.07.22 |
|---|---|
| STM32H757 User configuration (0) | 2024.07.22 |
| stm32h757xi / stm32h757i-eval (0) | 2024.07.19 |
| FT5336 - 정전식 터치 i2c (0) | 2021.07.06 |
| stm32f4 otg update bin file (0) | 2021.07.02 |
480MHz의 Coretx-M7 / Cortex-M4가 달려있는 듀얼 코어 cpu이다.
| Dual core • 32-bit Arm® Cortex®-M7 core with doubleprecision FPU and L1 cache: 16 Kbytes of data and 16 Kbytes of instruction cache; frequency up to 480 MHz, MPU, 1027 DMIPS/ 2.14 DMIPS/MHz (Dhrystone 2.1), and DSP instructions • 32-bit Arm® 32-bit Cortex®-M4 core with FPU, Adaptive real-time accelerator (ART Accelerator) for internal flash memory and external memories, frequency up to 240 MHz, MPU, 300 DMIPS/1.25 DMIPS /MHz (Dhrystone 2.1), and DSP instructions |
ART 가속에 대해서는 머라머라 써있는데 이해를 못하겠고..
대충 온칩 메모리(SRAM)과 플래시에 대해서 대기없는 접근이 가능하다 정도로 이해..
그런데 Cortex-M4 에만 달려서 테시등을 확인하는걸 보면.. M4 쪽이 slave 구성인가 싶기도 하다
| The acceleration is achieved by loading selected code into an embedded cache and making it instantly available to the Cortex-M4 core, thus avoiding latency due to memory wait states. ART™ accelerator features: • 32-bit AHB slave port to interface with the D2 domain • 32-bit AHB master port for non-cacheable memory accesses • 64-bit AXI master port to load the code from memory to cache • 64 cache lines of 256 bits • Fully-associative cache • Programmable cacheable page • Cache content consistency checker |
stm32h747xi 와 stm32h757xi 로 eval 보드가 있는데
두 칩 간 주요 차이점은 757은 암호화 모듈이 내장되어 있다는 것 정도?
D1 domain 에는 cortex-M7이 있는 것 같고. M7 에만 TCM(tightly coupled memory)가 달려있다.
D2 domain 에는 Cortex-M4가 있고 플래시가 없다? D1 domain으로 접근해서 Flash에서 펌웨어를 불러오게 되는 구조 같다.
D3 domain 에는 DBMA / SDRAM 64k / Backup SRAM 4k 가 있는데 얘는 절전모드 용인가?
AHB는 1<->2<->3 그리고 1<->3 간에 존재하여 어느쪽이던 많이 돌지 않고 접근이 가능하다.
부팅은 BOOT0 핀과 BOOT_ADDx 옵션 바이트에 의해서 결정되는데
BOOT0 핀이 0이면
CM7은 플래시의 0x0800_000을 사용하고
CM4는 플래시의 0x0810_000을 사용한다.
BCM4/7은 SYSCFG_UR1 레지스터에 존재하는 녀석인데 얜 어느 시점에 누가 설정하지?
| 3.2 Dual-core boot At startup, the boot memory space is selected by the BOOT pin and BOOT_ADDx option bytes, allowing to program any boot memory address from 0x0000 0000 to 0x3FFF FFFF which includes all Flash address space, all RAM address space (ITCM, DTCM RAMs and SRAMs) and the System memory bootloader. The boot address is provided by option byte and default programmed value to allow: • CM7 Boots from Flash memory at 0x0800 0000 when Boot0=0 • CM4 Boots from Flash memory at 0x0810 0000 when Boot0=0 • Boot respectively from System memory or SRAM1 when Boot0=1 The values on the BOOT pin are latched on the 4th rising edge of SYSCLK after reset release. It is up to the user to set the BOOT pin after reset as shown in the figure below. If the programmed boot memory address is out of the memory mapped area or a reserved area, the default boot fetch address is: • BCM7_ADD0: FLASH at 0x0800 0000 • BCM4_ADD0: FLASH at 0x0810 0000 • BCM7_ADD1: System Memory at 0x1FF0 0000 • BCM4_ADD1: SRAM1 at 0x1000 0000 When Flash level 2 protection is enabled, only boot from Flash or system is available. If boot address is out of the memory range or RAM address, then the default fetch is forced from Flash at address 0x0800 0000 for Cortex®‑M7 and Flash at address 0x0810 0000 for Cortex®-M4. In the STM32H7 dual‑core, to maximize energy efficiency, each core operates in its own power domain and can be turned off individually when not needed. The two cores can boot alone or in the same time according to the option bytes as shown in Table 4.  |
아니 최소한 하나의 문서에 어디라고 표기는 해달라고 -_ㅠ
477p - BOOT_C1 / BOOT_C2
601p - BCM7 / BCM4 reset value가 x면 도대체 머라고 해석해야 하지?
| STM32H757 User configuration (0) | 2024.07.22 |
|---|---|
| STM32CubeProgrammer (0) | 2024.07.22 |
| FT5336 - 정전식 터치 i2c (0) | 2021.07.06 |
| stm32f4 otg update bin file (0) | 2021.07.02 |
| stm32cubeide generate bin (0) | 2021.07.02 |
신호 발생기 통해서 넣어 보니 3.3V 에서 65535로 가득 찬다.
| raw | base | |
| 60398 | 65535 | 3.04132753490501 |
| 62367 | 65535 | 3.14047608148318 |
| 64319 | 65535 | 3.23876859693294 |
| 65535 | 65535 | 3.3 |
ADC 입력 범위는 0~3.3V 인 듯(음수도 넣어 볼 걸 그랬나..
GND의 경우 0 으로 뜨니 음수는 안될 것 같기도 한데 과연?
ADC가 12bit 인데 16bit 값으로 해서 0.05V 정도 오차가 생기는게 아닐까 싶긴 하다
(혹은 내부 AREF 회로에서 RC 회로로 구현해 오차가 발생한걸지도)
| rpi pico sdk (0) | 2025.03.23 |
|---|---|
| rpi pico usb joystick (0) | 2024.10.07 |
| rpi pico / micropython (0) | 2024.07.15 |
| rpi pico usb sound (0) | 2021.11.08 |
| rpi pico pwm channel (0) | 2021.08.02 |
circuit python 을 예전에 사용했었는데
circuit python 에서 import machine 하면 모듈이 없다고 해서 찾아보니
micropython 에서 제공하는 녀석이라고 한다.
| machine is a built-in module in MicroPython which means it's part of MicroPython itself. CircuitPython and MicroPython similar but not exactly the same. One difference is that CircuitPython has no built-in module called machine. |
[링크 : https://forums.raspberrypi.com/viewtopic.php?t=314090]
| rpi pico usb joystick (0) | 2024.10.07 |
|---|---|
| rpi pico ADC 범위 (0) | 2024.07.16 |
| rpi pico usb sound (0) | 2021.11.08 |
| rpi pico pwm channel (0) | 2021.08.02 |
| rpi pico c (0) | 2021.07.07 |
timer 설명에 설정값에 따라 GPIO 출력이 바뀌게 되는게 가능한건 알고 있었는데
그걸 어떻게 써먹나 어따 써먹다 이런게 안떠올라서 잊고 있던걸 구현된 코드를 처음으로 봄 -_-
IP로 구현된 통신이 아닌
GPIO를 통해 정확한 시간 간격에 오가야 한다면
타이머 값이 매치되면 값이 바뀌는게 가장 정확할 수 밖에 없겠구나 싶어진다.
[링크 : https://m.blog.naver.com/eziya76/221461279858]
[링크 : https://m.blog.naver.com/eziya76/222712447615]
[링크 : https://eteo.tistory.com/159]
| stm32f103 adc + dma (0) | 2024.11.04 |
|---|---|
| stm32 adc 읽기(1개로 여러 개 채널) (0) | 2024.10.30 |
| stm32 reset 없이 JTAG 붙이기 (0) | 2023.07.19 |
| STM32H/STM32G 시리즈 시리얼 포트 데이터 order (0) | 2022.08.29 |
| stm32 wdg 최대 설정시간 (0) | 2021.08.09 |
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