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'잡동사니'에 해당되는 글 13033건
- 2022.10.19 fftw 예제 와 복소수 처리
- 2022.10.19 tlv
- 2022.10.19 fftw 테스트(tests/bench)
- 2022.10.19 fftw cross compile
- 2022.10.19 RAMS
- 2022.10.18 linux fifo
- 2022.10.17 gdb 디버깅 타겟을 인자와 함께 실행하기
- 2022.10.17 SIGPIPE
- 2022.10.17 DR - Disaster Recovery Plan
- 2022.10.17 cpuid
프로그램 사용/fft, fftw2022. 10. 19. 20:07
이론 관련/컴퓨터 관련2022. 10. 19. 19:20
http://www.ktword.co.kr/test/view/view.php?m_temp1=3739
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| SLP - Superword Level Parallelism (0) | 2022.06.02 |
| digital twin (0) | 2022.04.13 |
프로그램 사용/fft, fftw2022. 10. 19. 15:19
도대체 저 옵션들은 먼지 모르겠다.
| fftw-3.3.4/tests/bench -o nthreads=2 --verbose=1 --verify 'ok10bx6bx6e11x13b' --verify 'ik10bx6bx6e11x13b' --verify 'obrd7x13v16' --verify 'ibrd7x13v16' --verify 'ofrd7x13v16' --verify 'ifrd7x13v16' --verify '//obcd7x13v16' --verify '//ibcd7x13v16' --verify '//ofcd7x13v16' --verify '//ifcd7x13v16' --verify 'obcd7x13v16' --verify 'ibcd7x13v16' --verify 'ofcd7x13v16' --verify 'ifcd7x13v16' --verify 'okd10bv127' --verify 'ikd10bv127' --verify '//obr240' --verify '//ibr240' --verify '//ofr240' --verify '//ifr240' --verify 'obr240' --verify 'ibr240' --verify 'ofr240' --verify 'ifr240' --verify '//obc240' --verify '//ibc240' --verify '//ofc240' --verify '//ifc240' --verify 'obc240' --verify 'ibc240' --verify 'ofc240' --verify 'ifc240' --verify 'ok11760e00' --verify 'ik11760e00' --verify 'obr33v31' --verify 'ibr33v31' --verify 'ofr33v31' --verify 'ifr33v31' --verify '//obc33v31' --verify '//ibc33v31' --verify '//ofc33v31' --verify '//ifc33v31' --verify 'obc33v31' --verify 'ibc33v31' |
[링크 : https://unix.stackexchange.com/questions/209753/how-do-i-check-if-fftw-installed-correctly]
+
[링크 : https://people.sc.fsu.edu/~jburkardt/c_src/fftw_test/]
[링크 : https://people.sc.fsu.edu/~jburkardt/c_src/fftw_test/fftw_test.html]
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프로그램 사용/fft, fftw2022. 10. 19. 12:33
[링크 : https://www.fftw.org/download.html]
| ./configure --prefix=/home/zhouxiaoyong/fftw3_test --disable-fortran --with-slow-timer --host=arm-none-linux-gnueabi --enable-single --enable-neon --enable-shared CC=arm-none-linux-gnueabi-gcc CFLAGS="-march=armv7-a -mfpu=neon -fPIC -ldl -mfloat-abi=softfp" |
[링크 : https://codeantenna.com/a/ztGG77F10Z]
| The basic usage of FFTW is simple. A typical call to FFTW looks like: #include <fftw.h> ... { fftw_complex in[N], out[N]; fftw_plan p; ... p = fftw_create_plan(N, FFTW_FORWARD, FFTW_ESTIMATE); ... fftw_one(p, in, out); ... fftw_destroy_plan(p); } For example, code to perform an in-place FFT of a three-dimensional array might look like: #include <fftw.h> ... { fftw_complex in[L][M][N]; fftwnd_plan p; ... p = fftw3d_create_plan(L, M, N, FFTW_FORWARD, FFTW_MEASURE | FFTW_IN_PLACE); ... fftwnd_one(p, &in[0][0][0], NULL); ... fftwnd_destroy_plan(p); } The following is a brief example in which the wisdom is read from a file, a plan is created (possibly generating more wisdom), and then the wisdom is exported to a string and printed to stdout. { fftw_plan plan; char *wisdom_string; FILE *input_file; /* open file to read wisdom from */ input_file = fopen("sample.wisdom", "r"); if (FFTW_FAILURE == fftw_import_wisdom_from_file(input_file)) printf("Error reading wisdom!\n"); fclose(input_file); /* be sure to close the file! */ /* create a plan for N=64, possibly creating and/or using wisdom */ plan = fftw_create_plan(64,FFTW_FORWARD, FFTW_MEASURE | FFTW_USE_WISDOM); /* ... do some computations with the plan ... */ /* always destroy plans when you are done */ fftw_destroy_plan(plan); /* write the wisdom to a string */ wisdom_string = fftw_export_wisdom_to_string(); if (wisdom_string != NULL) { printf("Accumulated wisdom: %s\n",wisdom_string); /* Just for fun, destroy and restore the wisdom */ fftw_forget_wisdom(); /* all gone! */ fftw_import_wisdom_from_string(wisdom_string); /* wisdom is back! */ fftw_free(wisdom_string); /* deallocate it since we're done */ } } |
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| fft (0) | 2020.11.25 |
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회사일2022. 10. 19. 12:09
Reliability(신뢰성)
Availability(가용성)
Maintainability(유지보수성)
Safety(안전성)
문서를 쓰려면 머리 아플, 테스트로 시간 엄청 들일 녀석이겠구나..
[링크 : http://www.daeati.co.kr/sub03_rams.php]
유럽 철도분야의 RAMS(Reliability, Availability, Maintainability, and Safety) 표준으로 제정한 EN50126은 시스템의 신뢰성, 가용성, 보전성 및 안전성에 대한 필수적인 요구사항을 규정하고 있다.
[링크 : https://scienceon.kisti.re.kr/srch/selectPORSrchArticle.do?cn=DIKO0010114980&dbt=DIKO]
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Linux API/linux2022. 10. 18. 18:20
특이하다면 특이하고, 당연하다면 당연하게
fifo는 쓸 녀석과, 읽을 녀석이 둘다 요청이 들어올때 까지 open() 에서 blocking 된다.
strace를 이용해서 확인해보면 각각 실행할 경우
O_RDONLY를 주던 O_WRONLY를 주던 간에 open() 함수에서 block 되어있다
두개 프로그램이 read/write pair가 만들어지면 그제서야 open()을 넘어가게 된다.
open()을 non_block 으로 해서 name pipe의 pair가 만들어지길 기다리는 것도 방법 일 듯.
| $ strace ./rx openat(AT_FDCWD, "/tmp/fifo", O_RDONLY |
$ strace ./tx 2 openat(AT_FDCWD, "/tmp/fifo", O_WRONLY |
[링크 : https://tutorialspoint.dev/computer-science/operating-systems/named-pipe-fifo-example-c-program]
걍 이렇게 하고 나서 해보면 되려나?
| int fifo_fd = open(fifo_path, O_RDONLY | O_NONBLOCK); FILE *fp = fdopen(fifo_fd, "r"); |
[링크 : https://cboard.cprogramming.com/c-programming/89358-nonblocking-fifo.html]
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프로그램 사용/gdb & insight2022. 10. 17. 17:58
예를 들어 ls -al을 하려면 아래와 같이 하면 된다.
| $ gdb --args ls -al |
그냥 넣으면 gdb의 옵션으로 해석한다.
| $ gdb ls -al gdb: 인식할 수 없는 옵션 '-al' Use `gdb --help' for a complete list of options. |
| $ gdb --args executablename arg1 arg2 arg3 |
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Linux API/linux2022. 10. 17. 17:56
mkfifo()를 이용하여 named pipe를 해보는데
받는 쪽이 사라지니 보내는 애가 갑자기 에러도 없이 죽어
gdb로 확인해보니 SIGPIPE가 전달되었고 그로 인해서 프로세스가 종료 된 것으로 보인다.
| Program received signal SIGPIPE, Broken pipe. 0x00007ffff7af2104 in __GI___libc_write (fd=3, buf=0x7ffff76e1010, nbytes=3145728) at ../sysdeps/unix/sysv/linux/write.c:27 27 ../sysdeps/unix/sysv/linux/write.c: 그런 파일이나 디렉터리가 없습니다. |
[링크 : https://jacking75.github.io/linux_socket_sigpipe/]
gdb 에서 무시하게 하려면 아래의 명령어를 입력하라고 한다.
| handle SIGPIPE nostop pass pass |
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이론 관련/컴퓨터 관련2022. 10. 17. 17:51
이번 카카오 사태에 갑자기 뜬(?) 용어
HA까지만 알았는데 DR은 솔찍히 첨 듣는다.
[링크 : https://en.wikipedia.org/wiki/Disaster_recovery]
[링크 : https://en.wikipedia.org/wiki/Business_continuity_planning]
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Linux/Ubuntu2022. 10. 17. 17:49
맨날
$ cat /proc/cpuinfo
로 확인했는데 편하게 보는 유틸리티가 있었다니..
| $ cpuid CPU 0: vendor_id = "GenuineIntel" version information (1/eax): processor type = primary processor (0) family = Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6) model = 0xe (14) stepping id = 0xc (12) extended family = 0x0 (0) extended model = 0x8 (8) (simple synth) = Intel m3-7Y00 / i5-7Y00 / i7-7Y00 / i3-7000U / i5-7000U / i7-7000U / Pentium 4410Y / 4415U / Celeron 3965Y / 3865U / 3965U (Kaby Lake), 14nm miscellaneous (1/ebx): process local APIC physical ID = 0x0 (0) cpu count = 0x10 (16) CLFLUSH line size = 0x8 (8) brand index = 0x0 (0) brand id = 0x00 (0): unknown feature information (1/edx): x87 FPU on chip = true virtual-8086 mode enhancement = true debugging extensions = true page size extensions = true time stamp counter = true RDMSR and WRMSR support = true physical address extensions = true machine check exception = true CMPXCHG8B inst. = true APIC on chip = true SYSENTER and SYSEXIT = true memory type range registers = true PTE global bit = true machine check architecture = true conditional move/compare instruction = true page attribute table = true page size extension = true processor serial number = false CLFLUSH instruction = true debug store = true thermal monitor and clock ctrl = true MMX Technology = true FXSAVE/FXRSTOR = true SSE extensions = true SSE2 extensions = true self snoop = true hyper-threading / multi-core supported = true therm. monitor = true IA64 = false pending break event = true feature information (1/ecx): PNI/SSE3: Prescott New Instructions = true PCLMULDQ instruction = true 64-bit debug store = true MONITOR/MWAIT = true CPL-qualified debug store = true VMX: virtual machine extensions = true SMX: safer mode extensions = false Enhanced Intel SpeedStep Technology = true thermal monitor 2 = true SSSE3 extensions = true context ID: adaptive or shared L1 data = false FMA instruction = true CMPXCHG16B instruction = true xTPR disable = true perfmon and debug = true process context identifiers = true direct cache access = false SSE4.1 extensions = true SSE4.2 extensions = true extended xAPIC support = true MOVBE instruction = true POPCNT instruction = true time stamp counter deadline = true AES instruction = true XSAVE/XSTOR states = true OS-enabled XSAVE/XSTOR = true AVX: advanced vector extensions = true F16C half-precision convert instruction = true RDRAND instruction = true hypervisor guest status = false cache and TLB information (2): 0x63: data TLB: 1G pages, 4-way, 4 entries 0x03: data TLB: 4K pages, 4-way, 64 entries 0x76: instruction TLB: 2M/4M pages, fully, 8 entries 0xff: cache data is in CPUID 4 0xb5: instruction TLB: 4K, 8-way, 64 entries 0xf0: 64 byte prefetching 0xc3: L2 TLB: 4K/2M pages, 6-way, 1536 entries processor serial number: 0008-06EC-0000-0000-0000-0000 deterministic cache parameters (4): --- cache 0 --- cache type = data cache (1) cache level = 0x1 (1) self-initializing cache level = true fully associative cache = false extra threads sharing this cache = 0x1 (1) extra processor cores on this die = 0x7 (7) system coherency line size = 0x3f (63) physical line partitions = 0x0 (0) ways of associativity = 0x7 (7) ways of associativity = 0x0 (0) WBINVD/INVD behavior on lower caches = false inclusive to lower caches = false complex cache indexing = false number of sets - 1 (s) = 63 --- cache 1 --- cache type = instruction cache (2) cache level = 0x1 (1) self-initializing cache level = true fully associative cache = false extra threads sharing this cache = 0x1 (1) extra processor cores on this die = 0x7 (7) system coherency line size = 0x3f (63) physical line partitions = 0x0 (0) ways of associativity = 0x7 (7) ways of associativity = 0x0 (0) WBINVD/INVD behavior on lower caches = false inclusive to lower caches = false complex cache indexing = false number of sets - 1 (s) = 63 --- cache 2 --- cache type = unified cache (3) cache level = 0x2 (2) self-initializing cache level = true fully associative cache = false extra threads sharing this cache = 0x1 (1) extra processor cores on this die = 0x7 (7) system coherency line size = 0x3f (63) physical line partitions = 0x0 (0) ways of associativity = 0x3 (3) ways of associativity = 0x0 (0) WBINVD/INVD behavior on lower caches = false inclusive to lower caches = false complex cache indexing = false number of sets - 1 (s) = 1023 --- cache 3 --- cache type = unified cache (3) cache level = 0x3 (3) self-initializing cache level = true fully associative cache = false extra threads sharing this cache = 0xf (15) extra processor cores on this die = 0x7 (7) system coherency line size = 0x3f (63) physical line partitions = 0x0 (0) ways of associativity = 0xf (15) ways of associativity = 0x6 (6) WBINVD/INVD behavior on lower caches = false inclusive to lower caches = true complex cache indexing = true number of sets - 1 (s) = 8191 MONITOR/MWAIT (5): smallest monitor-line size (bytes) = 0x40 (64) largest monitor-line size (bytes) = 0x40 (64) enum of Monitor-MWAIT exts supported = true supports intrs as break-event for MWAIT = true number of C0 sub C-states using MWAIT = 0x0 (0) number of C1 sub C-states using MWAIT = 0x2 (2) number of C2 sub C-states using MWAIT = 0x1 (1) number of C3 sub C-states using MWAIT = 0x2 (2) number of C4 sub C-states using MWAIT = 0x4 (4) number of C5 sub C-states using MWAIT = 0x1 (1) number of C6 sub C-states using MWAIT = 0x1 (1) number of C7 sub C-states using MWAIT = 0x1 (1) Thermal and Power Management Features (6): digital thermometer = true Intel Turbo Boost Technology = true ARAT always running APIC timer = true PLN power limit notification = true ECMD extended clock modulation duty = true PTM package thermal management = true HWP base registers = true HWP notification = true HWP activity window = true HWP energy performance preference = true HWP package level request = false HDC base registers = true digital thermometer thresholds = 0x2 (2) ACNT/MCNT supported performance measure = true ACNT2 available = false performance-energy bias capability = true extended feature flags (7): FSGSBASE instructions = true IA32_TSC_ADJUST MSR supported = true SGX: Software Guard Extensions supported = true BMI instruction = true HLE hardware lock elision = false AVX2: advanced vector extensions 2 = true FDP_EXCPTN_ONLY = false SMEP supervisor mode exec protection = true BMI2 instructions = true enhanced REP MOVSB/STOSB = true INVPCID instruction = true RTM: restricted transactional memory = false QM: quality of service monitoring = false deprecated FPU CS/DS = true intel memory protection extensions = true PQE: platform quality of service enforce = false AVX512F: AVX-512 foundation instructions = false AVX512DQ: double & quadword instructions = false RDSEED instruction = true ADX instructions = true SMAP: supervisor mode access prevention = true AVX512IFMA: fused multiply add = false CLFLUSHOPT instruction = true CLWB instruction = false Intel processor trace = true AVX512PF: prefetch instructions = false AVX512ER: exponent & reciprocal instrs = false AVX512CD: conflict detection instrs = false SHA instructions = false AVX512BW: byte & word instructions = false AVX512VL: vector length = false PREFETCHWT1 = false AVX512VBMI: vector byte manipulation = false UMIP: user-mode instruction prevention = false PKU protection keys for user-mode = false OSPKE CR4.PKE and RDPKRU/WRPKRU = false BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0) RDPID: read processor D supported = false SGX_LC: SGX launch config supported = false AVX512_4VNNIW: neural network instrs = false AVX512_4FMAPS: multiply acc single prec = false Direct Cache Access Parameters (9): PLATFORM_DCA_CAP MSR bits = 0 Architecture Performance Monitoring Features (0xa/eax): version ID = 0x4 (4) number of counters per logical processor = 0x4 (4) bit width of counter = 0x30 (48) length of EBX bit vector = 0x7 (7) Architecture Performance Monitoring Features (0xa/ebx): core cycle event not available = false instruction retired event not available = false reference cycles event not available = false last-level cache ref event not available = false last-level cache miss event not avail = false branch inst retired event not available = false branch mispred retired event not avail = false Architecture Performance Monitoring Features (0xa/edx): number of fixed counters = 0x3 (3) bit width of fixed counters = 0x30 (48) x2APIC features / processor topology (0xb): --- level 0 (thread) --- bits to shift APIC ID to get next = 0x1 (1) logical processors at this level = 0x2 (2) level number = 0x0 (0) level type = thread (1) extended APIC ID = 0 --- level 1 (core) --- bits to shift APIC ID to get next = 0x4 (4) logical processors at this level = 0x8 (8) level number = 0x1 (1) level type = core (2) extended APIC ID = 0 XSAVE features (0xd/0): XCR0 lower 32 bits valid bit field mask = 0x0000001f XCR0 upper 32 bits valid bit field mask = 0x00000000 XCR0 supported: x87 state = true XCR0 supported: SSE state = true XCR0 supported: AVX state = true XCR0 supported: MPX BNDREGS = true XCR0 supported: MPX BNDCSR = true XCR0 supported: AVX-512 opmask = false XCR0 supported: AVX-512 ZMM_Hi256 = false XCR0 supported: AVX-512 Hi16_ZMM = false IA32_XSS supported: PT state = false XCR0 supported: PKRU state = false bytes required by fields in XCR0 = 0x00000440 (1088) bytes required by XSAVE/XRSTOR area = 0x00000440 (1088) XSAVE features (0xd/1): XSAVEOPT instruction = true XSAVEC instruction = true XGETBV instruction = true XSAVES/XRSTORS instructions = true SAVE area size in bytes = 0x000003c0 (960) IA32_XSS lower 32 bits valid bit field mask = 0x00000100 IA32_XSS upper 32 bits valid bit field mask = 0x00000000 AVX/YMM features (0xd/2): AVX/YMM save state byte size = 0x00000100 (256) AVX/YMM save state byte offset = 0x00000240 (576) supported in IA32_XSS or XCR0 = XCR0 (user state) 64-byte alignment in compacted XSAVE = false MPX BNDREGS features (0xd/3): MPX BNDREGS save state byte size = 0x00000040 (64) MPX BNDREGS save state byte offset = 0x000003c0 (960) supported in IA32_XSS or XCR0 = XCR0 (user state) 64-byte alignment in compacted XSAVE = false MPX BNDCSR features (0xd/4): MPX BNDCSR save state byte size = 0x00000040 (64) MPX BNDCSR save state byte offset = 0x00000400 (1024) supported in IA32_XSS or XCR0 = XCR0 (user state) 64-byte alignment in compacted XSAVE = false PT features (0xd/8): PT save state byte size = 0x00000080 (128) PT save state byte offset = 0x00000000 (0) supported in IA32_XSS or XCR0 = IA32_XSS (supervisor state) 64-byte alignment in compacted XSAVE = false Quality of Service Monitoring Resource Type (0xf/0): Maximum range of RMID = 0 supports L3 cache QoS monitoring = false Resource Director Technology allocation (0x10/0): L3 cache allocation technology supported = false L2 cache allocation technology supported = false 0x00000011 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000 SGX capability (0x12/0): SGX1 supported = false SGX2 supported = false MISCSELECT.EXINFO supported: #PF & #GP = false MaxEnclaveSize_Not64 (log2) = 0x0 (0) MaxEnclaveSize_64 (log2) = 0x0 (0) 0x00000013 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000 Intel Processor Trace (0x14): IA32_RTIT_CR3_MATCH is accessible = true configurable PSB & cycle-accurate = true IP & TraceStop filtering; PT preserve = true MTC timing packet; suppress COFI-based = true PTWRITE support = false power event trace support = false IA32_RTIT_CTL can enable tracing = true ToPA can hold many output entries = true single-range output scheme = true output to trace transport = false IP payloads have LIP values & CS = false configurable address ranges = 0x2 (2) supported MTC periods bitmask = 0x249 (585) supported cycle threshold bitmask = 0x3fff (16383) supported config PSB freq bitmask = 0x3f (63) Time Stamp Counter/Core Crystal Clock Information (0x15): TSC/clock ratio = 192/2 nominal core crystal clock = 0 Hz Processor Frequency Information (0x16): Core Base Frequency (MHz) = 0x8fc (2300) Core Maximum Frequency (MHz) = 0x1324 (4900) Bus (Reference) Frequency (MHz) = 0x64 (100) extended feature flags (0x80000001/edx): SYSCALL and SYSRET instructions = true execution disable = true 1-GB large page support = true RDTSCP = true 64-bit extensions technology available = true Intel feature flags (0x80000001/ecx): LAHF/SAHF supported in 64-bit mode = true LZCNT advanced bit manipulation = true 3DNow! PREFETCH/PREFETCHW instructions = true brand = "Intel(R) Core(TM) i7-10510U CPU @ 1.80GHz" L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax): instruction # entries = 0x0 (0) instruction associativity = 0x0 (0) data # entries = 0x0 (0) data associativity = 0x0 (0) L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx): instruction # entries = 0x0 (0) instruction associativity = 0x0 (0) data # entries = 0x0 (0) data associativity = 0x0 (0) L1 data cache information (0x80000005/ecx): line size (bytes) = 0x0 (0) lines per tag = 0x0 (0) associativity = 0x0 (0) size (KB) = 0x0 (0) L1 instruction cache information (0x80000005/edx): line size (bytes) = 0x0 (0) lines per tag = 0x0 (0) associativity = 0x0 (0) size (KB) = 0x0 (0) L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax): instruction # entries = 0x0 (0) instruction associativity = L2 off (0) data # entries = 0x0 (0) data associativity = L2 off (0) L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx): instruction # entries = 0x0 (0) instruction associativity = L2 off (0) data # entries = 0x0 (0) data associativity = L2 off (0) L2 unified cache information (0x80000006/ecx): line size (bytes) = 0x40 (64) lines per tag = 0x0 (0) associativity = 8-way (6) size (KB) = 0x100 (256) L3 cache information (0x80000006/edx): line size (bytes) = 0x0 (0) lines per tag = 0x0 (0) associativity = L2 off (0) size (in 512KB units) = 0x0 (0) Advanced Power Management Features (0x80000007/edx): temperature sensing diode = false frequency ID (FID) control = false voltage ID (VID) control = false thermal trip (TTP) = false thermal monitor (TM) = false software thermal control (STC) = false 100 MHz multiplier control = false hardware P-State control = false TscInvariant = true Physical Address and Linear Address Size (0x80000008/eax): maximum physical address bits = 0x27 (39) maximum linear (virtual) address bits = 0x30 (48) maximum guest physical address bits = 0x0 (0) Logical CPU cores (0x80000008/ecx): number of CPU cores - 1 = 0x0 (0) ApicIdCoreIdSize = 0x0 (0) (multi-processing synth): multi-core (c=4), hyper-threaded (t=2) (multi-processing method): Intel leaf 0xb (APIC widths synth): CORE_width=4 SMT_width=1 (APIC synth): PKG_ID=0 CORE_ID=0 SMT_ID=0 (synth) = Intel m3-7Y00 / i5-7Y00 / i7-7Y00 / i3-7000U / i5-7000U / i7-7000U (Kaby Lake), 14nm |
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