Sipeed MAix BiT Kit for RISC-V AI+IoT
라는 제품에 들어있는 risc-v mcu의 성능을 보려는데 벤치마크에 어라..? FFT ?!
The Maix Bit is a low-cost development board from Sipeed, featuring the Kendryte K210 from Canaan.
The Kendryte K210 is an SoC that includes:
- Dual-core 64-bit RISC-V,
- KPU (Knowledge Processing Unit),
- APU (Audio Processing Unit),
- FFT (Fast Fourier Transform) accelerator,
- etc.
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[링크 : https://www.luffca.com/2021/10/maixpy-fft-maix-bit/]
데이터시트나
NPU, FFT, AES, SHA 가속기능이 있다. 특이하네..
그리고 KPU의 입력소스로서 영상 입력 기능(DVP). DVP가 LCD 출력도 겸하나?
1.1 Overview
Knowledge Processing Unit (KPU, aka Neural network Processing Unit).
KPU is a general-purpose neural network processor that implements convolutional
neural network calculations with low power consumption. It can acquire the size,
coordinates and types of detected objects in real time, and detect and classify
faces or objects. When using kpu, the neural network model must be generated with
the model compiler.
1.2 Features
KPU has the following characteristics:
• Supports the fixed training model that the common training framework trains
according to specific restriction rules
• There is no direct limit on the number of network layers, which supports separate configuration of each layer of convolutional neural network parameters,
including the number of input and output channels, input and output line width
and column height.
• Support for two convolution kernels 1x1 and 3x3
• Support for any form of activation function
• The maximum supported neural network parameter size in real-time work is
5.5MiB to 5.9MiB
• Maximum support network parameter size when working in non-real time is (Flash
capacity) - (software size)
2.1 Overview
Advanced Encryption Standard (AES) acceleration engine. The AES module uses hardware to implement AES operation acceleration.
2.2 Features
K210 have a built-in AES(Advanced Encryption Standard acceleration engine). Compared with software, it can greatly improve the speed of AES operation. The AES
accelerator supports multiple encryption/decryption modes (ECB, CBC, GCM) and multiple length of KEY (128, 192, 256).
7.1 Overview
Digital Video Port (DVP) unit is a camera interface unit that supports forwarding
camera input image data to KPU or memory.
7.2 Features
The DVP unit has the following features:
• Support RGB565, RGB422 and single channel Y gray scale input mode
• Support for setting frame interrupt
• Support setting transfer address
• Supports writing data to two addresses at the same time (output format is
RGB888 and RGB565 respectively)
• Support for discarding frames that do not need to be processed
8.1 Overview
Fast Fourier Transform (FFT) Accelerator.
The FFT accelerator implements the radix-2 decimation-in-time (DIT) Cooley–Tukey
FFT algorithm*
1 acceleration in hardware.
8.2 Features
The FFT accelerator currently supports 64-point, 128-point, 256-point, and 512-
point FFTs and IFFTs. Inside the FFT accelerator, there are two SRAMs with a size
of 512 * 32 bits. After the configuration is completed, the FFT sends a TX request
to the DMA, and the data sent by the DMA is placed in one of the SRAMs until the
data volume satisfies the current FFT operation needs, and the FFT operation begins at this point. The butterfly operation unit reads data from the SRAM which
containing the valid data, and writes the data to another SRAM after the end of the
operation. The next butterfly operation reads the data from the SRAM just written,
when the operation ends write to another SRAM. This process alternates this way
until the entire FFT operation is completed.
9.1 Overview
Secure Hash Algorithm (SHA) accelerator supports hardware acceleration of the
sha256 algorithm.
9.2 Features
• Supports hardware acceleration of the sha256 algorithm |
[링크 : https://www.canaan.io/wp-content/uploads/2020/02/kendryte_standalone_programming_guide_20190311144158_en.pdf]
[링크 : https://www.canaan.io/product/kendryteai]
