The Active Serial (AS) configuration scheme is supported in the 1 bit data width (AS x1) or the 4 bit data width (AS x4). The AS x4 scheme is supported only in Stratix® Vdevices. AS configuration can be performed using an Altera® serial configuration (EPCS) device or quad-serial configuration (EPCQ) device. During AS configuration, the Altera FPGA acts as the configuration master and the EPCS or EPCQ device acts as the configuration slave. The FPGA outputs the clock on the DCLK pin and receives the configuration data from the EPCS or EPCQ device on the data pin(s).
Passive serial (PS) configuration can be performed using an Altera® download cable, an Altera configuration device, or an intelligent host such as a microprocessor. During PS configuration, data is transferred from a configuration device, flash memory, or other storage device to the Altera device on the DATA0 pin. This configuration data is latched into the FPGA on the rising edge of DCLK. Configuration data is transferred at a rate of one bit per clock cycle.
