verilog module instantiate

정리 안해놨었나..?

왼쪽과 오른쪽이 혼용되서 쓰이는데

오른쪽은 C언어의 함수처럼, 변수(?)의 순서대로 선언하면 된다.

왼쪽은 구조체 변수 초기화 하는 느낌? 타이핑할 건 늘어나지만 순서대로 안해줘도 되니까

일장일단이 있다.(그래도 난 함수 처럼 순서대로 넣는게 편할 듯)

module dff (clk, d, q); input clk, d; output q; reg q; always @(posedge clk) q = d; endmodule   module top; reg data, clock; wire q_out, net_1;   dff inst_1 (.d(data), .q(net_1), .clk(clock));   dff inst_2 (.clk(clock), .d(net_1), .q(q_out)); endmodule

module dff (clk, d, q); input clk, d; output q; reg q; always @(posedge clk) q = d; endmodule   module top; reg data, clock; wire q_out, net_1;   dff inst_1 (clock, data, net_1);   dff inst_2 (clock, net_1, q_out); endmodule

순서대로 할 경우 ,, 으로 값을 넣지 않을수 있는데 이 경우 Hi-Z 로 설정이 된다.

(net 타입이니까 Hi-Z로 된다고 써있는 듯)

example 1 module dff (clk, d, q); input clk, d; output q; reg q; always @(posedge clk) q = d; endmodule   module top; reg data, clock; wire q_out, net_1;   dff inst_1 (.d(data), .q(net_1), .clk(clock));   dff inst_2 (.clk(clock), .d(net_1), .q(q_out)); endmodule In the top module there are two instantiations of the 'dff' module. In both cases port connections are done by name, so the port order is insignificant. The first port is input port 'd', the second is output 'q' and the last is the clock in the 'inst_1'. In the dff module the order of ports is different than either of the two instantiations. Example 2 module dff (clk, d, q); input clk, d; output q; reg q; always @(posedge clk) q = d; endmodule   module top; reg data, clock; wire q_out, net_1;   dff inst_1 (clock, data, net_1);   dff inst_2 (clock, net_1, q_out); endmodule Example 3 dff inst_1 (clock, , net_1); Second port is unconnected and has the value Z because it is of the net type. Example 4 module my_module (a, b, c); input a, b; output c;   assign c = a & b ; endmodule   module top (a, b, c) ; input [3:0] a, b; output [3:0] c;   my_module inst [3:0] (a, b, c); endmodule

[링크 : http://verilog.renerta.com/mobile/source/vrg00027.htm]

[링크 : https://en.wikibooks.org/wiki/Programmable_Logic/Verilog_Module_Structure]