구차니의 잡동사니 모음

Features:

• Xilinx Artix-35T FPGA:
  • 33,280 logic cells in 5200 slices (each slice contains four 6-input LUTs and 8 flip-flops);
  • 1,800 Kbits of fast block RAM;
  • Five clock management tiles, each with a phase-locked loop (PLL);
  • 90 DSP slices;
  • Internal clock speeds exceeding 450MHz;
  • On-chip analog-to-digital converter (XADC).
  • Programmable over JTAG and Quad-SPI Flash
• System Features:
  • 256MB DDR3L with a 16-bit bus @ 667MHz
  • 16MB Quad-SPI Flash
  • USB-JTAG Programming circuitry (USB Micro cable required, NOT INCLUDED). 
  • Powered from USB or any 7V-15V source
• System Connectivity:
  • 10/100 Mbps Ethernet
  • USB-UART Bridge
• Interaction and Sensory Devices
  • 4 Switches
  • 4 Buttons
  • 1 Reset Button
  • 4 LEDs
  • 4 RGB LEDs
• Expansion Connectors:
  • 4 Pmod connectors
  • Arduino/chipKIT Shield connector 

The bits are automatically swapped for all of the PROM formats: MCS, EXO, BIN and TEK. For a HEX file output, bit swapping is on by default, but it can be turned off by deselecting a Swap Bits option. 

Found the answer (http://quartushelp.altera.com/current/mergedProjects/reference/glossary/def_rbf.htm). It is LSB first. 

LUT, Logic Cell and Logic Element are all the same to me: the most basic FPGA general logic primitive. Xilinx use LUT, Altera LE, microsemi/lattice possibly something else.

The problem is, they are not the same. In their most recent architecture, Xilinx use 6-input LUT and altera 4-input LUT. They are aggregated in logic blocks which has other features like fast-carry chain, registers and distributed memory.

Converting to system gates is useful, but don't forget it's also a marketing war. A Xilinx FPGA should fit 1.5 times the logic of an Altera FPGA, since it's LUT have 6 instead of 4, right? Well, it largely depends on the design, if the design can't use 6-inputs much, the unused ones are wasted. Same with fast-carry logic, I don't know if they count that in equivalent gate number, but be advised that number is inflated.

System gates is a common measure of ASIC design complexity. The same design on two different foundries should have similar system gates number, as waste is not really an issue for ASIC.

If you're looking for an FPGA. I suggest you choose your vendor, port enough of your design to get an idea of how big a FPGA you need and choose a FPGA with an upgrade path (if you want to market). If it's for a single prototype, just use the biggest FPGA you can afford. 

Logic array blocks (LABs) contain groups of LEs. 

Each LAB consists of the following features: 

■ 16 LEs

High-performance FPGA fabric Enhanced 8-input ALM with four registers 

The PCIe endpoint support includes multifunction support for up to eight functions, as shown in the following figure. The integrated multifunction support reduces the FPGA logic requirements by up to 20,000 LEs for PCIe designs that require multiple peripherals. 

Designing the ALM The ALM is radically different from any other FPGA logic block, offering a number of major innovations. Getting from a classic 4-LUT with a single register block (with associated carry logic) to the ALM required a detailed understanding of customer requirements and a large investment in researching the tradeoffs of various architectures. Our pursuit for a larger LUT was inspired by research results indicating that a basic 6-LUT could yield a 14% performance improvement by reducing the number of levels of logic elements on the critical paths of circuits. Unfortunately, this performance increase also had a large area penalty, a 17% area increase resulting from a larger LUT-mask and more inputs for the LUT. Figure 4 illustrates the tradeoff between cost and delay for different sizes of LUTs. The basic approach in designing the ALM was to investigate building a larger LUT to reduce levels of logic and increase performance, but to also avoid the area increase by efficiently dividing the larger LUT into smaller LUTs when appropriate, as illustrated by the dashed line. The ability to divide a LUT is what makes it “adaptive.”  

Device Family Support:

• • Virtex UltraScale 
   
  • Kintex UltraScale 
  • Zynq-7000 
   
  • Virtex-7 
   
  • Kintex-7 
   
  • Artix-7 
  • Spartan-6 
   
  • Virtex-6 
   
  • Virtex-5 
   
  • Virtex-4 
  • Spartan-3
   

Nios II/e[edit]

The Nios II/e core is designed for smallest possible logic utilization of FPGAs. This is especially efficient for low-cost Cyclone II FPGA applications. Features of Nios II/e include:

• Up to 2 GB of external address space
• JTAG debug module
• Complete systems in fewer than 700 LEs
• Optional debug enhancements
• Up to 256 custom instructions
• Free, no license required 

• The Cyclone IV GX FPGA architecture consists of up to 150K vertically arranged logic elements (LEs), 6.5 Mbits of embedded memory arranged as 9-Kbit (M9K) blocks, and 360 18 x 18 embedded multipliers. New to the Cyclone series, Cyclone IV GX FPGAs feature integrated transceivers at up to 3.125 Gbps.
• The Cyclone IV E FPGA architecture consists of up to 115K vertically arranged LEs, 4 Mbits of embedded memory arranged as 9-Kbit (M9K) blocks, and 266 18 x 18 embedded multipliers.