버전을 넣어서 삭제하면 끝
| $ sudo apt purge segger-jlink-udev-rules st-stlink-server st-stlink-udev-rules st-stm32cubeide-1.5.0 |
[링크 : https://askubuntu.com/questions/1444347/uninstall-stm32cubeide]
| stm32cubeide 펌웨어 업데이트 이후 자동 재시작 (0) | 2024.07.25 |
|---|---|
| stm32cubeide(eclipse) project clean시 빌드 하지 않기 (0) | 2024.07.24 |
| STM32H7 디버깅 설정(cubeIDE) (0) | 2024.07.22 |
| STM32H750 operation mode (0) | 2024.07.22 |
| STM32 MPU(Memory Protection Unit) (0) | 2024.07.22 |
접속 시도해보니 안되길래
버전 확인
| phpPgAdmin 7.13.0 (PHP 8.2.7) |
postgresql은 아래와 같은데..
| $ psql --version psql (PostgreSQL) 15.7 ( 15.7-0+deb12u1) |
그래서 phpPgAdmin 버전으로 찾아보니..
7.13.0 이후로는 안나오는것 같고(2020년 11월 9일.. 4년 가까이 과거..)
그 당시 지원되는게 Postgres 13 / 14.. 15니 될리가 없었...나?
| phpPgAdmin 7.13.0 Now Available! Posted on 2020-11-09 by phpPgAdmin Project Related Open Source I’m pleased to announce the latest release of phpPgAdmin, version 7.13.0. This release incorporates the following changes: Add support for Postgres 13 Add provisional support for Postgres 14 Upgrade Jquery library to 3.4.1 (Nirgal) Allow users to see group owned databases when using “owned only” Fix bug where sorting on selects dumped you to the table screen (MichaMEG) |
[링크 : https://www.postgresql.org/about/news/phppgadmin-7130-now-available-2107/]
죽은 프로젝트 인 듯.. 걍 사용을 포기하는게 낫겠다..
| postgresql 리스트 명령 (0) | 2024.07.25 |
|---|---|
| postgresql permission denied for schema public (0) | 2024.07.25 |
| phppgadmin (0) | 2024.07.23 |
| postgresql 15.7 on rpi (0) | 2024.07.22 |
| postgresql cli (0) | 2024.07.21 |
pgadmin은 써봐도 phppgadmin은 첨인가...
[링크 : https://www.rosehosting.com/blog/how-to-install-phppgadmin-on-ubuntu-22-04/]
+
생각해보니 pgadmin 이라고 웹기반으로 하는 녀석이었지
phpmyadmin 처럼 apache에서 웹을 띄워서 하진 않았던 것 같다.
| postgresql permission denied for schema public (0) | 2024.07.25 |
|---|---|
| 라즈베리에 phppgadmin. 안되잖아? (0) | 2024.07.24 |
| postgresql 15.7 on rpi (0) | 2024.07.22 |
| postgresql cli (0) | 2024.07.21 |
| psql copy to (0) | 2020.02.10 |
예전에 해봤는데 안되길래 포기했던 녀석들..
이제는 시간이 지났으니 잘 되려나?
ssh -D
[링크 : https://superuser.com/questions/408031/differences-between-ssh-l-to-d]
wget은 socks proxy 미지원,curl 사용 필요
[링크 : https://askubuntu.com/questions/1327783/can-you-set-socks5-proxy-from-linux-command-line]
--proxy-server="socks5://myproxy:8080"
[링크 : https://www.chromium.org/developers/design-documents/network-stack/socks-proxy/]
[링크 : https://thesafety.us/proxy-setup-chrome-windows]
[링크 : https://datawookie.dev/blog/2023/12/ssh-tunnel-dynamic-port-forwarding/]
| ssh ecdsa 미지원(ubuntu 22.04) (0) | 2023.05.30 |
|---|---|
| ubuntu ssh x11 forwarding시 gnome 화면 끌어오기 (0) | 2022.07.11 |
| ssh 슈도 터미널 실행 (0) | 2022.04.25 |
| ssh Are you sure you want to continue connecting (yes/no)? (0) | 2022.04.25 |
| sshd 에서 ssh 로그인 끄고 sftp만 허용하기 (0) | 2022.04.01 |
Halt all cores 를 체크해서
Cortex-M7을 멈추면 Cortex-M4 도 같이 멈추고
Cortex-M4 에는 Halt 옵션이 없으니 M7을 멈출수 없어서 M4만 멈췄나 보다.
| stm32cubeide(eclipse) project clean시 빌드 하지 않기 (0) | 2024.07.24 |
|---|---|
| 우분투에서 stm32cubeide 삭제 (0) | 2024.07.24 |
| STM32H750 operation mode (0) | 2024.07.22 |
| STM32 MPU(Memory Protection Unit) (0) | 2024.07.22 |
| STM32 HSEM (Hardware SEMaphore) (0) | 2024.07.22 |
소스를 뒤져보면서 메뉴얼 찾아보는 중
stm32h7xx_hal_pwr_ex.c 파일에 보면 D3Domain 이라고 PWR_CPUCR_RUN_D3 라고
d3 도메인의 cpu (cortex-m4)를 살리는 녀석으로 보인다.
| void HAL_PWREx_ConfigD3Domain (uint32_t D3State) { /* Check the parameter */ assert_param (IS_D3_STATE (D3State)); /* Keep D3/SRD in run mode */ MODIFY_REG (PWR->CPUCR, PWR_CPUCR_RUN_D3, D3State); } |
| /******************** Bit definition for PWR_CPUCR register *****************/ #define PWR_CPUCR_RUN_D3_Pos (11U) #define PWR_CPUCR_RUN_D3_Msk (0x1UL << PWR_CPUCR_RUN_D3_Pos) /*!< 0x00000800 */ #define PWR_CPUCR_RUN_D3 PWR_CPUCR_RUN_D3_Msk /*!< Keep system D3 domain in RUN mode regardless of the CPU sub-systems modes */ /******************** Bit definition for PWR_CPU2CR register ****************/ #define PWR_CPU2CR_RUN_D3_Pos (11U) #define PWR_CPU2CR_RUN_D3_Msk (0x1UL << PWR_CPU2CR_RUN_D3_Pos) /*!< 0x00000800 */ #define PWR_CPU2CR_RUN_D3 PWR_CPU2CR_RUN_D3_Msk /*!< Keep system D3 domain in RUN mode regardless of the CPU sub-systems modes */ |
stm32h757xi.pdf 데이터 시트 31page
어.. D2 domain에 Cortex-M4 였네..
rm0399-stm32h745755-and-stm32h747757-advanced-armbased-32bit-mcus-stmicroelectronics.pdf
| 7.6.1 Operating modes Several system operating modes are available to tune the system according to the performance required, i.e. when the CPU(s) do not need to execute code and are waiting for an external event. It is up to the user to select the operating mode that gives the best compromise between low power consumption, short startup time and available wakeup sources. The operating modes allow controlling the clock distribution to the different system blocks and powering them. The system operating mode is driven by CPU1 subsystem, CPU2 subsystem and system D3 autonomous wakeup. A CPU subsystem can include multiple domains depending on its peripheral allocation (see Section 9.5.11: Peripheral clock gating control). The following operating modes are available for the different system blocks (see Table 34): • CPU subsystem modes: – CRun CPU and CPU subsystem peripheral allocated via RCC PERxEN bits are clocked. – CSleep: The CPU clocks is stalled and the CPU subsystem allocated peripheral(s) clock operate according to RCC PERxLPEN. – CStop: CPU and CPU subsystem peripheral clocks are stalled. • D1 domain and D2 domain modes: – DRun The domain bus matrix is clocked: - The domain CPU subsystem(a) is in CRun or CSleep mode, or - the other domain CPU subsystem(a) having an allocated peripheral in the domain is in CRun or CSleep mode. – DStop The domain bus matrix clock is stalled: - The domain CPU subsystem is in CStop mode and - The other domain CPU subsystem has no peripheral allocated in the domain. or the other domain CPU subsystem having an allocated peripheral in the domain is also in CStop mode and - At least one PDDS_Dn(b) bit for the domain select DStop. – DStandby The domain is powered down: - The domain CPU subsystem is in CStop mode and - The other domain CPU subsystem has no peripheral allocated in the domain or the other domain CPU subsystem having an allocated peripheral in the domain is also in CStop mode and - All PDDS_Dn(b) bits for the domain select DStandby mode. • System /D3 domain modes – Run/Run* The system clock and D3 domain bus matrix clock are running: - A CPU subsystem is in CRun or CSleep mode or - A wakeup signal is active. (i.e. System D3 autonomous mode) The Run* mode is entered after a POR reset and a wakeup from Standby. In Run* mode, the performance is limited and the system supply configuration shall be programmed in PWR control register 3 (PWR_CR3). The system enters Run mode only when the ACTVOSRDY bit in PWR control status register 1 (PWR_CSR1) is set to 1. – Stop The system clock and D3 domain bus matrix clock is stalled: - both CPU subsystems are in CStop mode. and - all wakeup signals are inactive. and - At least one PDDS_Dn(b) bit for any domain select Stop mode. – Standby The system is powered down: - both CPU subsystems are in CStop mode and - all wakeup signals are inactive. and - All PDDS_Dn(b) bits for all domains select Standby mode. In Run mode, power consumption can be reduced by one of the following means: •Lowering the system performance by slowing down the system clocks and reducing the VCORE supply level through VOS voltage scaling bits. •Gating the clocks to the APBx and AHBx peripherals when they are not used, through PERxEN bits. a. The domain CPU subsystem, for example CPU1 subsystem for D1 domain. a. The other domain CPU subsystem, for example CPU1 subsystem for D2 domain. |
| 9 Reset and Clock Control (RCC) The RCC block manages the clock and reset generation for the whole microcontroller, which embeds two CPUs: an Arm® Cortex®-M7 and an Arm® Cortex®-M4, called CPU1 and CPU2, respectively. The RCC block is located in the D3 domain (refer to Section 7: Power control (PWR) for a detailed description). The operating modes this section refers to are defined in Section 7.6.1: Operating modes of the PWR block. |
cpu1 power 용
cpu2 power 용. 서로 접근하면 되나?
| 우분투에서 stm32cubeide 삭제 (0) | 2024.07.24 |
|---|---|
| STM32H7 디버깅 설정(cubeIDE) (0) | 2024.07.22 |
| STM32 MPU(Memory Protection Unit) (0) | 2024.07.22 |
| STM32 HSEM (Hardware SEMaphore) (0) | 2024.07.22 |
| STM32H757 User configuration (0) | 2024.07.22 |
MMU 처럼 메모리 관리하는건 아니고, 메모리 접근을 관리하는 녀석인듯.
| This application note describes how to manage the memory protection unit (MPU) in the STM32 products The MPU is an optional component for the memory protection. Including the MPU in the STM32 microcontrollers (MCUs) makes them more robust and reliable. The MPU must be programmed and enabled before using it. If the MPU is not enabled, there is no change in the memory system behavior. This application note concerns all the STM32 products listed in Table 1 that include the Cortex®-M0+/M3/M4 and M7 design that supports the MPU. For more details about the MPU, refer to the following documents available on http://www.st.com • Programming manual STM32F7 series and STM32H7 series Cortex®-M7 processor (PM0253) • Programming manual STM32F10xxx/20xxx/21xxx/L1xxxx Cortex®-M3 (PM0056) • Programming manual STM32 Cortex®-M0+ MCUs programming manual (PM0223) • Programming manual STM32 Cortex®-M4 MCUs and MPUs (PM0214) • Programming manual STM32 Cortex®-M33 MCUs (PM0264) Table 1. Applicable products Type Product series Microcontrollers • STM32C0 series • STM32F1 series, STM32F2 series, STM32F3 series, STM32F4 series, STM32F7 series • STM32G0 series, STM32G4 series • STM32H5 series, STM32H7 series • STM32L0 series, STM32L1 series, STM32L4 series, STM32L4+ series, STM32L5 series • STM32U0 series, STM32U5 series • STM32WB series, STM32WB0 series |
MPU는 2개 있고, 각각의 CPU에 대해서 메모리 접근을 확인한다고.
꽤 중요한 녀석인데 데이터시트에 고작 아래의 내용이 전부냐?!
| 3.2 Memory protection unit (MPU) The devices feature two memory protection units. Each MPU manages the CPU access rights and the attributes of the system resources. It has to be programmed and enabled before use. Its main purposes are to prevent an untrusted user program to accidentally corrupt data used by the OS and/or by a privileged task, but also to protect data processes or read-protect memory regions. The MPU defines access rules for privileged accesses and user program accesses. It allows defining up to 16 protected regions that can in turn be divided into up to 8 independent subregions, where region address, size, and attributes can be configured. The protection area ranges from 32 bytes to 4 Gbytes of addressable memory. When an unauthorized access is performed, a memory management exception is generated. |
[링크 : https://www.st.com/resource/en/datasheet/stm32h757ai.pdf]
| STM32H7 디버깅 설정(cubeIDE) (0) | 2024.07.22 |
|---|---|
| STM32H750 operation mode (0) | 2024.07.22 |
| STM32 HSEM (Hardware SEMaphore) (0) | 2024.07.22 |
| STM32H757 User configuration (0) | 2024.07.22 |
| STM32CubeProgrammer (0) | 2024.07.22 |
multi CPU를 위한 하드웨어 세마포어 인듯.
그러니까.. 싱글 코어이거나, 이기종 CPU가 아니라면 달려있는 이유가 없는 모듈
[링크 : https://www.st.com/resource/en/product_training/STM32WB-System-Hardware-Semaphore-HSEM.pdf]
| STM32H750 operation mode (0) | 2024.07.22 |
|---|---|
| STM32 MPU(Memory Protection Unit) (0) | 2024.07.22 |
| STM32H757 User configuration (0) | 2024.07.22 |
| STM32CubeProgrammer (0) | 2024.07.22 |
| stm32h757xi / stm32h757i-eval (0) | 2024.07.19 |
또 사라지는 해피빈이 생겨난다고 알람이 와서 기부.
가끔 광고 눌러서 받는 해피빈이라. 돈 안들이고 생색내는 기분.
| 티스토리 수익예측 (1) | 2024.09.11 |
|---|---|
| 이번주는 개발자들 휴가? (0) | 2024.07.31 |
| 티스토리 vs 브라우저 누구 탓이냐? (0) | 2024.07.18 |
| 도메인 결제의 달이 돌아왔습니다 (0) | 2024.06.03 |
| 당신의 이야기가 값진 수익이 됩니다 (2) | 2024.05.30 |
이전에 메뉴얼 뒤지다 발견한 BCM7/BCM4는 어디서 접근이 가능한지, 설정이 가능한지 찾질 못했는데
프로그램 하나 설치하니 해피하게 해결.. -_-
왼쪽 세번째 아이콘 OB가 Option Bytes 인데
거기서 User Configuration 항목에 BCM4 / BCM7을 발견할 수 있다.
[링크 : https://blog.naver.com/chandong83/221652968153]
[링크 : https://www.st.com/en/development-tools/stm32cubeprog.html]
[링크 : https://blog.naver.com/chcbaram/221597488638]
+
| HAL_FLASH_Unlock(); HAL_FLASH_OB_Unlock(); HAL_FLASHEx_OBGetConfig(&OBInit); OBInit.OptionType = OPTIONBYTE_CM7_BOOTADD; OBInit.BootAddr0 = 0x08010000; OBInit.BootConfig = OB_BOOT_ADD0; HAL_FLASHEx_OBProgram(&OBInit); HAL_FLASH_OB_Launch() |
[링크 : https://community.st.com/t5/stm32-mcus-products/stm32h745-set-cm7-boot-addr0-from-cm4/td-p/654791]
+
| void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) { pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_BOR; /*Get WRP*/ pOBInit->WRPSector = FLASH_OB_GetWRP(); /*Get RDP Level*/ pOBInit->RDPLevel = FLASH_OB_GetRDP(); /*Get USER*/ pOBInit->USERConfig = FLASH_OB_GetUser(); /*Get BOR Level*/ pOBInit->BORLevel = FLASH_OB_GetBOR(); } |
| typedef struct { uint32_t OptionType; /*!< Option byte to be configured. This parameter can be a value of @ref FLASHEx_Option_Type */ uint32_t WRPState; /*!< Write protection activation or deactivation. This parameter can be a value of @ref FLASHEx_WRP_State */ uint32_t WRPSector; /*!< Specifies the sector(s) to be write protected. The value of this parameter depend on device used within the same series */ uint32_t Banks; /*!< Select banks for WRP activation/deactivation of all sectors. This parameter must be a value of @ref FLASHEx_Banks */ uint32_t RDPLevel; /*!< Set the read protection level. This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */ uint32_t BORLevel; /*!< Set the BOR Level. This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */ uint8_t USERConfig; /*!< Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. */ } FLASH_OBProgramInitTypeDef; |
| STM32 MPU(Memory Protection Unit) (0) | 2024.07.22 |
|---|---|
| STM32 HSEM (Hardware SEMaphore) (0) | 2024.07.22 |
| STM32CubeProgrammer (0) | 2024.07.22 |
| stm32h757xi / stm32h757i-eval (0) | 2024.07.19 |
| FT5336 - 정전식 터치 i2c (0) | 2021.07.06 |
|
