구차니의 잡동사니 모음

 always @ (posedge clk or negedge rst)

begin

if (~rst)

cnt <= 0;

else

begin

if(cnt < 834000)

cnt <= cnt + 1;

else

cnt <= 0;

end

if(cnt < HSYNC)

hsync <= 1;

else hsync <= 0;

if(cnt < VSYNC)

vsync <= 1;

else vsync <= 0;

end

 always @ (posedge clk or negedge rst)

begin

if (~rst)

cnt <= 0;

else

begin

if(cnt < 834000)

begin

cnt <= cnt + 1;

if(cnt < HSYNC)

hsync <= 1;

else hsync <= 0;

if(cnt < VSYNC)

vsync <= 1;

else vsync <= 0;

end

else

cnt <= 0;

end

end

"VGA industry standard" 640x480 pixel mode

Clock frequency 25.175 MHz

Line  frequency 31469 Hz

Field frequency 59.94 Hz

One line

  8 pixels front porch

96 pixels horizontal sync

 40 pixels back porch

  8 pixels left border

640 pixels video

  8 pixels right border

---

800 pixels total per line

One field

  2 lines front porch

  2 lines vertical sync

 25 lines back porch

  8 lines top border

480 lines video

  8 lines bottom border

---

525 lines total per field               

//=======================================================

//  This code is generated by Terasic System Builder

//=======================================================

module PwmCtrl(RST_N, CLK, LED0);

input RST_N, CLK;

output LED0;

reg[27:0] counter0;

always @(negedge RST_N or posedge CLK)

begin

if(RST_N == 1'b0)

begin

counter0 <= 0;

end else begin

counter0 <= counter0 + 1;

end

end

assign LED0 = counter0[26];

endmodule

module DE0_NANO(

//////////// CLOCK //////////

CLOCK_50,

//////////// LED //////////

LED,

//////////// KEY //////////

KEY 

);

//=======================================================

//  PARAMETER declarations

//=======================================================

//=======================================================

//  PORT declarations

//=======================================================

//////////// CLOCK //////////

input           CLOCK_50;

//////////// LED //////////

output      [7:0] LED;

//////////// KEY //////////

input      [1:0] KEY;

//=======================================================

//  REG/WIRE declarations

//=======================================================

//=======================================================

//  Structural coding

//=======================================================

PwmCtrl pwm(KEY[0],

CLOCK_50,

LED[0]);

endmodule 

To enable the TalkBack feature in Quartus Prime, select Tools > Options. In the Options window, select Internet Connectivity from the menu, and click on TalkBack Options... to open the window shown in Figure 2. If you accept the TalkBack License Agreement, then check the box labelled Enable sending TalkBack data to Intel and click OK. 

Intel Quartus Prime Pro Edition software does not support the following Intel Quartus Prime Standard Edition features:

— I/O Timing Analysis

— NativeLink third party tool integration

— Video and Image Processing Suite IP Cores

— Talkback features

— Various register merging and duplication settings

— Saving a node-level netlist as .vqm

— Compare project revisions 

2016.10.31 16.1.0

Removed all references to Talkback feature.

Changed instances of Altera to Intel FPGA. 

※ Quartus Prime Lite Edition の場合は、16.0 以前のバージョンを使用する際 TalkBack 機能を有効にする 必要があります。詳細はこちらの TIPS をご覧ください。 

Quartus Prime Lite Edition의 경우 16.0 이전 버전을 사용하는 경우 TalkBack 기능을 활성화해야합니다. 자세한 것은 이쪽의 TIPS를 참조하십시오.