구차니의 잡동사니 모음

The TimeQuest timing analyzer is a powerful ASIC-style timing analysis tool that validates the timing performance of all logic in a design using industry standard constraint, analysis, and reporting methodology 

Synopsis Design Constraints (SDC)

tool command language (Tcl)

 Intel FPGAs must operate in a continuum of conditions. 

 These conditions include the die junction temperature, which varies depending upon the design's requirements. Commercial parts have a legal range of 0°C to 85°C and industrial parts have a legal range of -40°C to 100°C. There are even wider temperature ranges, such as those for automotive and military devices. 

 Another aspect of the operating conditions is the voltage supply levels. The most critical voltages for maintaining FPGA performance is the Vcc and the various I/O supplies. Each of the supply voltages has a legal operating range. For example, a subset of Stratix® IV FPGAs has a valid Vcc range of 0.87 V to 0.93 V. 

 The third aspect of the operating conditions is the relative speed of each FPGA versus the limit of the speed grade with which it is marked. This is one aspect that the designer has no control over. It should also be noted that devices within one speed grade can still differ slightly in performance, predominantly due to variation in the manufacturing process. All devices, however, are guaranteed to be faster than the limit of the speed grade.

• 3.1Compute (Nova)
• 3.2Networking (Neutron)
• 3.3Block storage (Cinder)
• 3.4Identity (Keystone)
• 3.5Image (Glance)
• 3.6Object storage (Swift)
• 3.7Dashboard (Horizon)
• 3.8Orchestration (Heat)
• 3.9Workflow (Mistral)
• 3.10Telemetry (Ceilometer)
• 3.11Database (Trove)
• 3.12Elastic map reduce (Sahara)
• 3.13Bare metal (Ironic)
• 3.14Messaging (Zaqar)
• 3.15Shared file system (Manila)
• 3.16DNS (Designate)
• 3.17Search (Searchlight)
• 3.18Key manager (Barbican)
• 3.19Container orchestration (Magnum)
• 3.20Root Cause Analysis (Vitrage)
• 3.21Rule-based alarm actions (Aodh)

module vga640x480(

input clk,

input rst,

output [7:0] LED,

output reg hsync,

output reg vsync,

output [3:0] r,

output [3:0] g,

output [3:0] b

);

reg clk25;

reg [9:0] horizontal_counter;

reg [9:0] vertical_counter;

reg [9:0] X;

reg [9:0] Y;

wire [7:0] red;

wire [7:0] green;

wire [7:0] blue;

initial

begin

horizontal_counter = 0;

vertical_counter = 0;

end

assign r[3:0] = ((horizontal_counter >= 144) 

&& (horizontal_counter < 784) 

&& (vertical_counter >=39)

&& (vertical_counter < 519)) ? red : 4'b000; 

assign g[3:0] = ((horizontal_counter >= 144) 

&& (horizontal_counter < 784) 

&& (vertical_counter >=39)

&& (vertical_counter < 519)) ? green : 4'b000; 

assign b[3:0] = ((horizontal_counter >= 144) 

&& (horizontal_counter < 784) 

&& (vertical_counter >=39)

&& (vertical_counter < 519)) ? blue : 4'b000; 

assign red =   ((horizontal_counter >= 144)&&(horizontal_counter < 344) ) ? 4'b1111 : 4'b0000;

assign green = ((horizontal_counter >= 344)&&(horizontal_counter < 544) ) ? 4'b1111 : 4'b0000;

assign blue =  ((horizontal_counter >= 544)&&(horizontal_counter < 784) ) ? 4'b1111 : 4'b0000;

always @(posedge clk)

begin

if (clk25 == 0)

begin

   clk25 <= 1;

end   

else

begin

clk25 <= 0;

   end

end

always @(posedge clk25)

begin

if ((horizontal_counter > 0) && (horizontal_counter < 97))// -- 96+1

begin

hsync <= 0;

end

else

begin

hsync <= 1;

end 

if ((vertical_counter > 0 ) && (vertical_counter < 3 )) //-- 2+1

begin

vsync <= 0;

end

else

begin

vsync <= 1;

end

horizontal_counter <= horizontal_counter+1;

if (horizontal_counter == 800) 

begin

vertical_counter <= vertical_counter+1;

horizontal_counter <= 0;

end

if (vertical_counter == 521)

begin

vertical_counter <= 0;

end

end

endmodule  

3.4.4 Measuring time

In wave viewer, select from top menus Add -> Cursor. Now you'll see 2 vertical lines (cursors). You can easily drag them and see the time interval between on the bottom. This is very handy when have to measure the execution time (or signal frequency). Just divide the time with the duration of a clock period to derive the number of clock cycles. 

module vga640x480(

input clk,

input rst,

output [7:0] LED,

output hsync,

output vsync,

output [3:0] r,

output [3:0] g,

output [3:0] b

);

parameter HSYNC = 190;

parameter HBP = (190 + 96);

parameter HVID = (190 + 96 + 1271);

parameter HFP = (190 + 96 + 1271 + 32);

parameter HTOTAL = 1589;

parameter VSYNC = 3200;

parameter VBP = (3200 + 52400);

parameter VVID = (3200 + 52400 + 762650);

parameter VFP = (3200 + 52400 + 762650 + 15900);

parameter VTOTAL = 834150;

reg [19:0] cnt;

always @ (posedge clk or negedge rst)

begin

if (~rst)

cnt <= 0;

else

begin

if(cnt < VTOTAL) cnt <= cnt + 1;

else cnt <= 0;

end

end

assign LED[0] = ~vsync;

assign LED[1] = ~hsync;

assign r[3:0] = (((VBP < cnt) && (cnt < VVID)) && ((HBP < (cnt % HTOTAL)) && ((cnt % HTOTAL) < HVID))) ? 4'b1111 : 4'b0000;

assign g[3:0] = (((VBP < cnt) && (cnt < VVID)) && ((HBP < (cnt % HTOTAL)) && ((cnt % HTOTAL) < HVID))) ? 4'b1111 : 4'b0000;

assign b[3:0] = (((VBP < cnt) && (cnt < VVID)) && ((HBP < (cnt % HTOTAL)) && ((cnt % HTOTAL) < HVID))) ? 4'b1111 : 4'b0000;

assign hsync = ((cnt % HTOTAL) < HSYNC)? 0 : 1;

assign vsync = ((cnt         ) < VSYNC)? 0 : 1;

endmodule