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vga640x480 vga(

CLOCK_50,

KEY[0],

LED,

GP0[6],

GP0[5],

{GP0[16],GP0[19],GP0[18],GP0[21]},

{GP0[12],GP0[15],GP0[14],GP0[17]},

{GP0[8],GP0[9],GP0[10],GP0[13]}

); 

module vga640x480(

input clk,

input rst,

output [7:0] LED,

output hsync,

output vsync,

output [3:0] r,

output [3:0] g,

output [3:0] b

);

parameter HSYNC = 189;

parameter HBP = (HSYNC + 95);

parameter HVID = (HBP + 1260);

parameter HFP = (HVID + 47);

parameter VSYNC = 3000;

parameter VBP = (VSYNC + 51000);

parameter VVID = (VBP + 762500);

parameter VFP = (VVID + 17500);

reg [19:0] cnt;

always @ (posedge clk or negedge rst)

begin

if (!rst)

begin

cnt <= 0;

end

else

begin

cnt <= cnt + 1;

if(cnt > 834000)

cnt <= 0;

end

end

assign hsync = ((cnt % 1590) < 189) ? 0 : 1;

assign vsync = (cnt < 3000) ? 0 : 1;

assign r = ((hsync & vsync) == 1 ? 4'b1111 : 4'b0000);

assign g = ((hsync & vsync) == 1 ? 4'b1111 : 4'b0000);

assign b = ((hsync & vsync) == 1 ? 4'b1111 : 4'b0000);

assign LED[0] = ~vsync;

assign LED[1] = ~hsync;

endmodule 

module vga800x600x60(

input clk,

input rst,

output [7:0] LED,

output hsync,

output vsync,

output [3:0] r,

output [3:0] g,

output [3:0] b

);

parameter HSYNC = 160;

parameter HBP = (HSYNC + 95);

parameter HVID = (HBP + 1260);

parameter HFP = (HVID + 47);

parameter VSYNC = 5300;

parameter VBP = (VSYNC + 51000);

parameter VVID = (VBP + 762500);

parameter VFP = (VVID + 17500);

reg [19:0] cnt;

always @ (posedge clk or negedge rst)

begin

if (!rst)

begin

cnt <= 0;

end

else

begin

cnt <= cnt + 1;

if(cnt > 828950)

cnt <= 0;

end

end

assign hsync = ((cnt % 1320) < 160) ? 0 : 1;

assign vsync = (cnt < 5300) ? 0 : 1;

assign r = ((hsync & vsync) == 1 ? 4'b1111 : 4'b0000);

assign g = ((hsync & vsync) == 1 ? 4'b1111 : 4'b0000);

assign b = ((hsync & vsync) == 1 ? 4'b1111 : 4'b0000);

assign LED[0] = ~vsync;

assign LED[1] = ~hsync;

endmodule  

For VESA 800*600 @ 60Hz: 

Fh (kHz) :37.88 

A (us) :26.4 

B (us) :3.2 

C (us) :2.2 

D (us) :20.0 

E (us) :1.0 

Fv (Hz) :60.32 

O (ms) :16.579 

P (ms) :0.106 

Q (ms) :0.607 

R (ms) :15.84 

S (ms) :0.026 

vga640x480 vga(

CLOCK_50,

KEY[0],

LED,

GP0[6],

GP0[5],

{GP0[16],GP0[19],GP0[18],GP0[21]},

{GP0[12],GP0[15],GP0[14],GP0[17]},

{GP0[8],GP0[9],GP0[10],GP0[13]}

); 

module vga640x480(

input clk,

input rst,

output [7:0] LED,

output reg hsync,

output reg vsync,

output [3:0] r,

output [3:0] g,

output [3:0] b

);

reg clk25;

reg [9:0] horizontal_counter;

reg [9:0] vertical_counter;

reg [9:0] X;

reg [9:0] Y;

wire [7:0] red;

wire [7:0] green;

wire [7:0] blue;

assign r[3:0] = ((horizontal_counter >= 144) 

&& (horizontal_counter < 784) 

&& (vertical_counter >=39)

&& (vertical_counter < 519)) ? 4'b1111 : 4'b000; 

assign g[1:0] = ((horizontal_counter >= 144) 

&& (horizontal_counter < 784) 

&& (vertical_counter >=39)

&& (vertical_counter < 519)) ? 4'b1111 : 4'b000; 

assign b[2:0] = ((horizontal_counter >= 144) 

&& (horizontal_counter < 784) 

&& (vertical_counter >=39)

&& (vertical_counter < 519)) ? 4'b1111 : 4'b000; 

assign red =   ((horizontal_counter >= 144)&&(horizontal_counter < 344) ) ? 4'b1111 : 4'b0000;

assign green = ((horizontal_counter >= 344)&&(horizontal_counter < 544) ) ? 4'b1111 : 4'b0000;

assign blue =  ((horizontal_counter >= 544)&&(horizontal_counter < 784) ) ? 4'b1111 : 4'b0000;

always @(posedge clk)

begin

if (clk25 == 0)

begin

   clk25 <= 1;

end   

else

begin

clk25 <= 0;

   end

end

always @(posedge clk25)

begin

if ((horizontal_counter > 0) && (horizontal_counter < 97))// -- 96+1

begin

hsync <= 0;

end

else

begin

hsync <= 1;

end 

if ((vertical_counter > 0 ) && (vertical_counter < 3 )) //-- 2+1

begin

vsync <= 0;

end

else

begin

vsync <= 1;

end

horizontal_counter <= horizontal_counter+1;

if (horizontal_counter == 800) 

begin

vertical_counter <= vertical_counter+1;

horizontal_counter <= 0;

end

if (vertical_counter == 521)

begin

vertical_counter <= 0;

end

end

endmodule  

vga_demo vga(

CLOCK_50,

KEY[0],

GP0[16],

GP0[12],

GP0[8],

GP0[6],

GP0[5],

); 

/*

VGA Demo 800x600 at 72Hz

http://www-mtl.mit.edu/Courses/6.111/labkit/vga.shtml

800x600, 72Hz 50.000 800 56 120 64 600 37 6 23

Pixel Clock (MHz): 50.000 

Horizontal (in Pixels)

    Active Video: 800 (16us)

    Front Porch:   56 (1.12us)

    Sync Pulse:   120 (2.4us)

    Back Porch:    64 (1.28us)

        Total pixel clock ticks: 1040 (20.8us)

Vertical (in Lines, so x20.8us)

    Active Video: 600 (12480us)

    Front Porch:   37 (769.6us)

    Sync Pulse:     6 (124.8us)

    Back Porch:    23 (478.4us)

        Total pixel clock ticks: 666 (13.32us)

Total pixel clock ticks: 692,640

50,000,000 / 692,640 = 72.187572188 = 72Hz

1 pixel clock = 1/50Mhz = 20ns = 0.02us

*/

module vga_demo

    (

        CLOCK_50,

        RESET,

        VGA_RED,

        VGA_GREEN,

        VGA_BLUE,

        VGA_HS,

        VGA_VS

    );

    input CLOCK_50;

    input RESET;

    output VGA_RED;

    output VGA_GREEN;

    output VGA_BLUE;

    output VGA_HS;

    output VGA_VS;

    /* Internal registers for horizontal signal timing */

    reg [10:0] hor_reg; // to count 1040 different values up to 1039

    reg hor_sync;

    wire hor_max = (hor_reg == 1039); // to tell when a line is full

    /* Internal registers for vertical signal timing */

    reg [9:0] ver_reg; // to count 666 different values up to 665

    reg ver_sync;

    reg red, green, blue;

    wire ver_max = (ver_reg == 665); // to tell when a line is full

    // Code

    /* Running through line */

    always @ (posedge CLOCK_50 or posedge RESET) begin

        if (RESET) begin 

            hor_reg <= 0;

            ver_reg <= 0;

        end

        else if (hor_max) begin

            hor_reg <= 0;

            /* Running through frame */

            if (ver_max)

                ver_reg <= 0;

            else

            ver_reg <= ver_reg + 1;

        end else

            hor_reg <= hor_reg + 1;

    end

    always @ (posedge CLOCK_50 or posedge RESET) begin

        if (RESET) begin 

            hor_sync <= 0;

            ver_sync <= 0;

        end

        else begin

            /* Generating the horizontal sync signal */

            if (hor_reg == 856)      // video (800) + front porch (56)

                hor_sync <= 1;       // turn on horizontal sync pulse

            else if (hor_reg == 976) // video (800) + front porch (56) + Sync Pulse (120)

                hor_sync <= 0;       // turn off horizontal sync pulse

            /* Generating the vertical sync signal */

            if (ver_reg == 637)      // LINES: video (600) +  front porch (37)

                ver_sync <= 1;       // turn on vertical sync pulse

            else if (ver_reg == 643) // LINES: video (600) + front porch (37) + Sync Pulse (6)

                ver_sync <= 0;       // turn off vertical sync pulse

            // Draw a single square.

            if (hor_reg >= 100 && hor_reg <= 200 && ver_reg >= 100 && ver_reg <= 200) begin

                red <= 1;

                green <= 0;

                blue <= 0;

            end 

            else begin

                red <= 1;

                green <= 1;

                blue <= 1;

            end

        end

    end

    // Send the sync signals to the output, inverted as the sync pulse is low.

    // Maybe wrong as this doc says pulse id positive http://tinyvga.com/vga-timing/800x600@72Hz

    assign VGA_HS = ~hor_sync;

    assign VGA_VS = ~ver_sync;

    // Send a pattern of colours (based on the registry bits) but do not output anything during the synchronization periods

    //assign VGA_RED = (!hor_reg[0] && !ver_reg[0] && ver_reg < 600 && hor_reg < 800);

    //assign VGA_GREEN = (!hor_reg[1] && !ver_reg[1] && ver_reg < 600 && hor_reg < 800);

    //assign VGA_BLUE = (!hor_reg[2] && !ver_reg[2] && ver_reg < 600 && hor_reg < 800);

    assign VGA_RED =  red && ver_reg < 600 && hor_reg < 800;

    assign VGA_GREEN = green && ver_reg < 600 && hor_reg < 800;

    assign VGA_BLUE = blue && ver_reg < 600 && hor_reg < 800;    

    // http://gerfficient.com/2013/02/11/fpga-to-vga-using-de0-nano/

endmodule 

게이트-레벨시뮬레이션은타이밍시뮬레이션에서 기능적결과의차이만을확인한다. 만약게이트-레벨시뮬레 이션은문제없고타이밍시뮬레이션이실패했다면, 넷리스트 가아닌타이밍으로발생된부분임을나타낸다. 백-어노테이트 타이밍 시뮬레이션은 타이밍 정보가 있는 게이트-레벨 시뮬레이션이다. 이를 위해 FPGA 벤더는 VITAL (VHDL Gate Level) 넷리스트 또는 Verilog 넷리스 트를 생성한다 

vga640x480 vga(

CLOCK_50,

KEY[0],

LED,

GP0[6],

GP0[5],

{GP0[16],GP0[19],GP0[18],GP0[21]},

{GP0[12],GP0[15],GP0[14],GP0[17]},

{GP0[8],GP0[9],GP0[10],GP0[13]}

); 

module vga640x480(

input clk,

input rst,

output [7:0] LED,

output reg hsync,

output reg vsync,

output [3:0] r,

output [3:0] g,

output [3:0] b

);

parameter HSYNC = 189;

parameter HBP = (HSYNC + 95);

parameter HVID = (HBP + 1260);

parameter HFP = (HVID + 47);

parameter VSYNC = 3000;

parameter VBP = (VSYNC + 51000);

parameter VVID = (VBP + 762500);

parameter VFP = (VVID + 17500);

reg [19:0] cnt;

always @ (posedge clk or negedge rst)

begin

if (~rst)

cnt <= 0;

else

begin

if(cnt < 834000)

begin

cnt <= cnt + 1;

if((cnt % 1590) < HSYNC)

hsync <= 1;

else hsync <= 0;

if(cnt < VSYNC)

vsync <= 1;

else vsync <= 0;

end

else

cnt <= 0;

end

end

assign LED[0] = vsync;

assign LED[1] = hsync;

endmodule 

module vga640x480(

input clk,

input rst,

output [7:0] LED,

output reg hsync,

output reg vsync,

output reg [3:0] r,

output reg [3:0] g,

output reg [3:0] b

);

parameter HSYNC = 189;

parameter HBP = (HSYNC + 95);

parameter HVID = (HBP + 1260);

parameter HFP = (HVID + 47);

parameter VSYNC = 3000;

parameter VBP = (VSYNC + 51000);

parameter VVID = (VBP + 762500);

parameter VFP = (VVID + 17500);

reg [19:0] cnt;

always @ (posedge clk or negedge rst)

begin

if (~rst)

begin

cnt <= 0;

hsync <= 1;

vsync <= 1;

end

else

begin

if(cnt < 834000)

begin

cnt <= cnt + 1;

if((cnt % 1590) < HSYNC)

hsync <= 0;

else hsync <= 1;

if(cnt < VSYNC)

vsync <= 0;

else vsync <= 1;

if(vsync & hsync)

begin

r <= 4'b1111;

g <= 4'b1111;

b <= 4'b1111;

end

else

begin

r <= 4'b0000;

g <= 4'b0000;

b <= 4'b0000;

end

end

else

cnt <= 0;

end

end

assign LED[0] = ~vsync;

assign LED[1] = ~hsync;

endmodule 

 always @ (posedge clk or negedge rst)

begin

if (~rst)

cnt <= 0;

else

begin

if(cnt < 834000)

cnt <= cnt + 1;

else

cnt <= 0;

end

if(cnt < HSYNC)

hsync <= 1;

else hsync <= 0;

if(cnt < VSYNC)

vsync <= 1;

else vsync <= 0;

end

 always @ (posedge clk or negedge rst)

begin

if (~rst)

cnt <= 0;

else

begin

if(cnt < 834000)

begin

cnt <= cnt + 1;

if(cnt < HSYNC)

hsync <= 1;

else hsync <= 0;

if(cnt < VSYNC)

vsync <= 1;

else vsync <= 0;

end

else

cnt <= 0;

end

end