embeded/esp322026. 2. 5. 09:59

윈도우용 인스톨러 보려는데 5.x 만 지원하고, 6.x 를 쓰려면 다른 gui 인스톨러 써보라고 한다. -_-

[링크 : https://dl.espressif.com/dl/esp-idf/?idf=4.3]

 

내가 필요로 하는건 4.3인데 vscode 에서 깔아 보라고 한다. 흐음..

[링크 : https://e8ch.tistory.com/21]

 

5.x 아니면 윈도우는 포기하는게 나을지도?

'embeded > esp32' 카테고리의 다른 글

idf.py help  (0) 2026.02.10
idf 프로젝트 생성하기  (0) 2026.02.08
esp32 와 ili9341 direction  (0) 2026.01.23
esp32-wroom-32 보드 / arduino 개발툴  (0) 2026.01.23
esp32-2432S028 데모 빌드  (0) 2026.01.21
Posted by 구차니
embeded/Cortex-M4 STM2026. 2. 4. 17:12

일단 코드 상으로는 FAST는 안 먹어서 찾아봐야겠고, doubleword 로만 써진다.

 

일단은 DBANK는 체크되어 있는게 기본값이고

 

bank1에 0802000에 쓰니 쓰여지긴 한데 64bit wide라서 의도한대로 딱딱 붙어있지 않고 4byte씩 띄엄띄엄 써진다.

 

해당 페이지 삭제하려고 했는데 0x0802 0000이 아닌 0x0804 0000 이고

체크하고 삭제하면 삭제되었다고 메시지는 뜨지만

 

정작 해당 위치를 다시 가면 내용이 남아있다.

그 와중에 0x0804 0000 위치로 가면 비어있는걸로 나온다.

 

먼가 이상한데.. 머가 이상한거라고 딱찝어 말하기 힘드네..

 

CubeProgrammer를 버전업해봐야하나? 2.21 버전이 최신이었던것 같은데..

 

2.21.0 흐음... 

[링크 : https://www.st.com/en/development-tools/stm32cubeprog.html]

 

+

웃긴게 sdk 문제인지

bank 2에 page 0 대신

bank 1 에 page 64로 하면 잘된다. 머냐?

'embeded > Cortex-M4 STM' 카테고리의 다른 글

NUCLEO-WL55JC  (0) 2026.03.17
stm32g473 ART accelerator on/off ?  (0) 2026.02.06
STM32G47x dual bank flash  (0) 2026.02.03
STM32F429I-DISC1 with lvgl  (0) 2026.02.03
32F469IDISCOVERY with lvgl  (0) 2026.02.02
Posted by 구차니
embeded/Cortex-M7 STM2026. 2. 3. 18:19

페이지라고 해야하나.. 아무튼 섹터별로 용량이 균등하지 않은 녀석도 있다.

 

그리고 듀얼 뱅크와 싱글 뱅크의 경우 일종의 raid 0 처럼 분할해서 striping 되어 저장된다.

[링크 : https://www.st.com/resource/en/application_note/an4826-stm32f7-series-flash-memory-dual-bank-mode-stmicroelectronics.pdf]

'embeded > Cortex-M7 STM' 카테고리의 다른 글

stm32h757 링커 스크립트  (0) 2026.03.13
stm32h757 메모리(SRAM) 구조  (0) 2026.03.13
stm32f746g-disco with semtech sx1276 and lvgl  (0) 2026.02.03
modbus rtu coil read  (0) 2024.10.10
stm32 __weak  (0) 2024.10.08
Posted by 구차니
embeded/Cortex-M4 STM2026. 2. 3. 17:58

플래시가 연속된 주소가 아니게 보인다.

63번 0x0801 F800

64번 0x0804 0000 신기하네..

 

Option Byte 에는 BFB2 / DBANK 등이 처음보는 녀석이고..

 

내용은 좀 더 봐야 할 듯.

ART/MIF 를 통해서 NVM Bank 1 / 2에 접근하는거라면.. ART를 그럼 사실상 강제하게 되는건가?

 

서로 다른 채널에 read / write 를 동시에 할 수 있다가 dual bank 의 장점인가?

The dual bank memory can be configured and used as a single large NVM block with continuous addressing (with few exceptions, not covered in this document). There are significant advantages when the NVM is configured to serve as two parallel blocks, the most important is the possibility to write on one bank without interrupting reading (and fetching instructions) from the other bank. This is the most important prerequisite to perform the updates without breaking the execution of the code from the program NVM.

[링크 : https://www.st.com/resource/en/application_note/an4767-onthefly-firmware-update-for-dual-bank-stm32-microcontrollers-stmicroelectronics.pdf]

 

Option byte의 DBANK 설정에 따라서

뱅크를 1개 쓰냐 2개 쓰냐인데

0으로 하면 싱글 뱅크, 4 Kbyte Page * 128 이 되고

1으로 하면 듀얼 뱅크, 2 Kbyte Page * 128 * 2가 되는건가?

 

ART를 켜면 올라가는걸 보면 일단 높은 수치가 성능이 좋은거 같은데,

ART OFF 에서 Single Bank가 성능이 더 좋은다고 보면되나?

[링크 : https://www.st.com/resource/en/product_training/STM32G4-Memory-Flash_FLASH.pdf]

 

+

2026.02.04

심심해서(?) DBANK 풀고

 

내부 플래시 구조를 보니

개별 페이지(?)당 용량은 2배로 늘고

총 페이지는 절반으로 줄어들었다.

'embeded > Cortex-M4 STM' 카테고리의 다른 글

stm32g473 ART accelerator on/off ?  (0) 2026.02.06
stm32g473 flash doubleword  (0) 2026.02.04
STM32F429I-DISC1 with lvgl  (0) 2026.02.03
32F469IDISCOVERY with lvgl  (0) 2026.02.02
UM2195 audio streaming Expansion Package for STM32Cube  (0) 2026.01.05
Posted by 구차니
embeded/Cortex-M7 STM2026. 2. 3. 12:31

액정은 큰 거 치고는 해상도가 낮다.

그래도 PSP 해상도라고(!) 130,560 pixel 이고 320x240의 76,800 pixel 에 비하면 거의 2배에 가까운 나름(!) 고해상도다.

  • STM32F746NGH6 Arm® Cortex® core-based microcontroller with 1 Mbyte of Flash memory and 340 Kbytes of RAM, in BGA216 package
  • 4.3” RGB 480×272 color LCD-TFT with capacitive touch screen
  • Ethernet compliant with IEEE-802.3-2002
  • USB OTG HS
  • USB OTG FS
  • SAI audio codec
  • Two ST-MEMS digital microphones
  • 128-Mbit Quad-SPI Flash memory
  • 128-Mbit SDRAM (64 Mbits accessible)

[링크 : https://www.st.com/en/evaluation-tools/32f746gdiscovery.html]

 

이건 또 어떻게 살리냐..

[링크 : https://www.semtech.com/products/wireless-rf/lora-connect/sx1276mb1las]

 

일단 이거부터 빌드해서 넣어보자!

[링크 : https://github.com/lvgl/lv_port_stm32f746_disco]

 

응~ 에러

라는데 웃긴건 elf 파일이 생성되어 있다.

arm-none-eabi-gcc -o "lv_port_stm32f746_disco.elf" @"objects.list"   -mcpu=cortex-m7 -T"/home/falinux/work/src/lv_port_stm32f746_disco/LinkerScript.ld" --specs=nosys.specs -Wl,-Map="lv_port_stm32f746_disco.map" -Wl,--gc-sections -static --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -Wl,--start-group -lc -lm -Wl,--end-group
/opt/st/stm32cubeide_1.16.0/plugins/cohttp://m.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.linux64_1.0.200.202406132123/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/bin/ld: warning: /opt/st/stm32cubeide_1.16.0/plugins/cohttp://m.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.linux64_1.0.200.202406132123/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+fp/hard/crtn.o: missing .note.GNU-stack section implies executable stack
/opt/st/stm32cubeide_1.16.0/plugins/cohttp://m.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.linux64_1.0.200.202406132123/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/bin/ld: NOTE: This behaviour is deprecated and will be removed in a future version of the linker
/opt/st/stm32cubeide_1.16.0/plugins/cohttp://m.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.linux64_1.0.200.202406132123/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/bin/ld: warning: lv_port_stm32f746_disco.elf has a LOAD segment with RWX permissions
Finished building target: lv_port_stm32f746_disco.elf
 
arm-none-eabi-size  lv_port_stm32f746_disco.elf 
   text    data     bss     dec     hex filename
 617604    1064  204368  823036   c8efc lv_port_stm32f746_disco.elf
Finished building: default.size.stdout
arm-none-eabi-objdump -h -S lv_port_stm32f746_disco.elf  > "lv_port_stm32f746_disco.list"
 
arm-none-eabi-objcopy  -O binary lv_port_stm32f746_disco.elf  "lv_port_stm32f746_disco.bin"
Finished building: lv_port_stm32f746_disco.bin
 
Finished building: lv_port_stm32f746_disco.list
 

12:38:35 Build Failed. 1 errors, 2 warnings. (took 53s.960ms)

 

cortex-m7 이라 기대했는데 해상도 때문인가 느리다?!

 

 

'embeded > Cortex-M7 STM' 카테고리의 다른 글

stm32h757 메모리(SRAM) 구조  (0) 2026.03.13
stm32f7 dual bank flash  (0) 2026.02.03
modbus rtu coil read  (0) 2024.10.10
stm32 __weak  (0) 2024.10.08
stm32 modbus  (0) 2024.09.26
Posted by 구차니
embeded/Cortex-M4 STM2026. 2. 3. 11:30

그냥 받아서 하니 잘된다.

 

git clone https://github.com/littlevgl/stm32f429_disco_no_os_sw4stm32.git --recurse-submodules

[링크 : https://github.com/lvgl/lv_port_stm32f429_disco]

 

회사에 굴러 다니던게 있었을 줄이야 -_-

[링크 : https://www.st.com/en/evaluation-tools/32f429idiscovery.html]

 

  • Core: Arm® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from flash memory, frequency up to 180 MHz, MPU, 225 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
  • Memories
    • 512 bytes of OTP memory
    • Up to 2 MB of flash memory organized into two banks allowing read-while-write
    • Up to 256+4 KB of SRAM including 64 KB of CCM (core coupled memory) data RAM
    • Flexible external memory controller with up to 32-bit data bus: SRAM, PSRAM, SDRAM/LPSDR SDRAM, compact flash/NOR/NAND memories
  • LCD parallel interface, 8080/6800 modes
  • LCD-TFT controller with fully programmable resolution (total width up to 4096 pixels, total height up to 2048 lines and pixel clock up to 83 MHz)
  • Chrom-ART Accelerator™ for enhanced graphic content creation (DMA2D)

[링크 : https://www.st.com/en/microcontrollers-microprocessors/stm32f429zi.html]

 

그나저나 main 함수 엄청 단촐하다.

int main(void)
{

HAL_Init();

/* Configure the system clock to 180 MHz */
SystemClock_Config();

/*Start up indication*/
BSP_LED_Init(LED3);
uint32_t i;
for (i = 0; i < 8; i++) {
BSP_LED_Toggle(LED3);
HAL_Delay(50);
}

lv_init();

tft_init();
touchpad_init();

// lv_example_scroll_3();
// lv_example_chart_7();

lv_demo_widgets();

while (1)
{
HAL_Delay(3);
lv_task_handler();
}
}

 

 

빌드하니 생각외로 용량은 적게 나온다. 이미지는 어떻게 처리한거지?

 

'embeded > Cortex-M4 STM' 카테고리의 다른 글

stm32g473 flash doubleword  (0) 2026.02.04
STM32G47x dual bank flash  (0) 2026.02.03
32F469IDISCOVERY with lvgl  (0) 2026.02.02
UM2195 audio streaming Expansion Package for STM32Cube  (0) 2026.01.05
stm32g4 cordic fmac  (0) 2025.11.28
Posted by 구차니
embeded/Cortex-M4 STM2026. 2. 2. 17:55

곧 다뤄보게 될 예정.

STM32F469 high-performance MCUs with ARM®Cortex®-M4 core and Chrom-ART Accelerator™
4 inches 800x480 pixel TFT color LCD with MIPI DSI interface and capacitive touch screen

[링크 : https://www.st.com/en/evaluation-tools/32f469idiscovery.html#overview]

 

spi가 아니라 dsi 라서 걱정했는데 다행히(!) 누군가가 benchmark 포팅해서 올려놔서 좀 날로 먹을수 있을 듯.

[링크 : https://github.com/lvgl/lv_port_stm32f469_disco/tree/master]

'embeded > Cortex-M4 STM' 카테고리의 다른 글

STM32G47x dual bank flash  (0) 2026.02.03
STM32F429I-DISC1 with lvgl  (0) 2026.02.03
UM2195 audio streaming Expansion Package for STM32Cube  (0) 2026.01.05
stm32g4 cordic fmac  (0) 2025.11.28
STM32CubeProgrammer / uart / parity  (0) 2025.11.28
Posted by 구차니
embeded/Cortex-M3 STM2026. 1. 29. 15:48

pc13번 언급이 있어서 확인해보니 RTC_OUT / RTC_TAMPER로 설정이 가능하다.

 

Tamper를 활성화 하면 RTC_OUT 에서 RTC Output on the Tamper pin이 사용 불가능해진다.

 

Tamper는 인터럽트가 있는걸 봐서는.. 일종의 input 으로 설정되나보다.

 

rtc_Tamper를 rtc out으로 쓰지 않으면, 기본으로 tamper는 disble 되는 듯

stm32f1xx_hal_rtc.c

  *** Tamper configuration ***
  ============================
  [..]
    (+) Enable the RTC Tamper and configure the Tamper Level using the
        HAL_RTCEx_SetTamper() function. You can configure RTC Tamper with interrupt
        mode using HAL_RTCEx_SetTamper_IT() function.
    (+) The TAMPER1 alternate function can be mapped to PC13


/**
  * @brief  Initializes the RTC peripheral
  * @param  hrtc   pointer to a RTC_HandleTypeDef structure that contains
  *                the configuration information for RTC.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
{
  /* Set Initialization mode */
  if (RTC_EnterInitMode(hrtc) != HAL_OK)
  {
    /* Set RTC state */
    hrtc->State = HAL_RTC_STATE_ERROR;

    return HAL_ERROR;
  }
  else
  {
    /* Clear Flags Bits */
    CLEAR_BIT(hrtc->Instance->CRL, (RTC_FLAG_OW | RTC_FLAG_ALRAF | RTC_FLAG_SEC));

    if (hrtc->Init.OutPut != RTC_OUTPUTSOURCE_NONE)
    {
      /* Disable the selected Tamper pin */
      CLEAR_BIT(BKP->CR, BKP_CR_TPE);
    }

    /* Set the signal which will be routed to RTC Tamper pin*/
    MODIFY_REG(BKP->RTCCR, (BKP_RTCCR_CCO | BKP_RTCCR_ASOE | BKP_RTCCR_ASOS), hrtc->Init.OutPut);
  }
}

 

stm32f1xx_hal_rtc.h

/** @defgroup RTC_output_source_to_output_on_the_Tamper_pin Output source to output on the Tamper pin
  * @{
  */

#define RTC_OUTPUTSOURCE_NONE               0x00000000U                       /*!< No output on the TAMPER pin  */
#define RTC_OUTPUTSOURCE_CALIBCLOCK         BKP_RTCCR_CCO                     /*!< RTC clock with a frequency divided by 64 on the TAMPER pin  */
#define RTC_OUTPUTSOURCE_ALARM              BKP_RTCCR_ASOE                    /*!< Alarm pulse signal on the TAMPER pin  */
#define RTC_OUTPUTSOURCE_SECOND             (BKP_RTCCR_ASOS | BKP_RTCCR_ASOE) /*!< Second pulse signal on the TAMPER pin  */

'embeded > Cortex-M3 STM' 카테고리의 다른 글

Mbed studio on ubuntu 22.04  (0) 2026.02.23
stm32f103c8t6 cpp std::cout 실패  (0) 2026.02.18
stm32f103 rtc backup register  (0) 2026.01.29
stm32 hal rcc flag  (0) 2026.01.27
stm32 ivt  (0) 2026.01.27
Posted by 구차니
embeded/Cortex-M3 STM2026. 1. 29. 14:39

rtc에 백업 레지스터라고 해서, software reset 걸려도 살아남는게 있다고 ai가 이야기 하길래 검색

rtc 활성화 하고나니 아래 초기화 코드가 추가되서 따라가서 보면 평범한(?) HAL_RTC_Init() 이 있고

/**
  * @brief RTC Initialization Function
  * @param None
  * @retval None
  */
static void MX_RTC_Init(void)
{

  /* USER CODE BEGIN RTC_Init 0 */

  /* USER CODE END RTC_Init 0 */

  /* USER CODE BEGIN RTC_Init 1 */

  /* USER CODE END RTC_Init 1 */

  /** Initialize RTC Only
  */
  hrtc.Instance = RTC;
  hrtc.Init.AsynchPrediv = RTC_AUTO_1_SECOND;
  hrtc.Init.OutPut = RTC_OUTPUTSOURCE_ALARM;
  if (HAL_RTC_Init(&hrtc) != HAL_OK)
  {
    Error_Handler();
  }
  /* USER CODE BEGIN RTC_Init 2 */

  /* USER CODE END RTC_Init 2 */

}

 

HAL_RTC_MspInit()을 통해

stm32f1xx_hal_rtc.c

    (+) To write to the RTC Backup Data registers, use the HAL_RTCEx_BKUPWrite()
        function.
    (+) To read the RTC Backup Data registers, use the HAL_RTCEx_BKUPRead()
        function.

/**
  * @brief  Initializes the RTC peripheral
  * @param  hrtc   pointer to a RTC_HandleTypeDef structure that contains
  *                the configuration information for RTC.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
{
  uint32_t prescaler = 0U;
  /* Check input parameters */
  if (hrtc == NULL)
  {
    return HAL_ERROR;
  }

  /* Check the parameters */
  assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));
  assert_param(IS_RTC_CALIB_OUTPUT(hrtc->Init.OutPut));
  assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv));

#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
#else
  if (hrtc->State == HAL_RTC_STATE_RESET)
  {
    /* Allocate lock resource and initialize it */
    hrtc->Lock = HAL_UNLOCKED;

    /* Initialize RTC MSP */
    HAL_RTC_MspInit(hrtc);
  }
}

/**
  * @brief  Initializes the RTC MSP.
  * @param  hrtc   pointer to a RTC_HandleTypeDef structure that contains
  *                the configuration information for RTC.
  * @retval None
  */
__weak void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc)
{
  /* Prevent unused argument(s) compilation warning */
  UNUSED(hrtc);
  /* NOTE : This function Should not be modified, when the callback is needed,
            the HAL_RTC_MspInit could be implemented in the user file
   */
}

 

백업 레지스터에 접근할수 있도록 풀어준다.
Core/Src/stm32f1xx_hal_msp.c

/**
* @brief RTC MSP Initialization
* This function configures the hardware resources used in this example
* @param hrtc: RTC handle pointer
* @retval None
*/
void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
{
  if(hrtc->Instance==RTC)
  {
  /* USER CODE BEGIN RTC_MspInit 0 */

  /* USER CODE END RTC_MspInit 0 */
    HAL_PWR_EnableBkUpAccess();
    /* Enable BKP CLK enable for backup registers */
    __HAL_RCC_BKP_CLK_ENABLE();
    /* Peripheral clock enable */
    __HAL_RCC_RTC_ENABLE();
  /* USER CODE BEGIN RTC_MspInit 1 */

  /* USER CODE END RTC_MspInit 1 */

  }

}

 

CR_DBP_BB 라는 레지스터에 활성화 해주는것 코드 느낌. 무슨 레지스터인지 따라가긴 귀찮으니 패스

stm32f1xx_hal_pwr.c

/**
  * @brief  Enables access to the backup domain (RTC registers, RTC
  *         backup data registers ).
  * @note   If the HSE divided by 128 is used as the RTC clock, the
  *         Backup Domain Access should be kept enabled.
  * @retval None
  */
void HAL_PWR_EnableBkUpAccess(void)
{
  /* Enable access to RTC and backup registers */
  *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE;
}

/**
  * @brief  Disables access to the backup domain (RTC registers, RTC
  *         backup data registers).
  * @note   If the HSE divided by 128 is used as the RTC clock, the
  *         Backup Domain Access should be kept enabled.
  * @retval None
  */
void HAL_PWR_DisableBkUpAccess(void)
{
  /* Disable access to RTC and backup registers */
  *(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE;
}

 

아무튼 백업레지스터 접근이 허용되면

HAL_RTCEx_BKUPWrite() 를 통해 쓰고

HAL_RTCEx_BKUPRead() 를 통해 읽을 수 있다.

stm32f1xx_hal_rtc_ex.c

/**
  * @brief  Writes a data in a specified RTC Backup data register.
  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
  *                the configuration information for RTC.
  * @param  BackupRegister: RTC Backup data Register number.
  *          This parameter can be: RTC_BKP_DRx where x can be from 1 to 10 (or 42) to
  *                                 specify the register (depending devices).
  * @param  Data: Data to be written in the specified RTC Backup data register.
  * @retval None
  */
void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
{
  uint32_t tmp = 0U;

  /* Prevent unused argument(s) compilation warning */
  UNUSED(hrtc);

  /* Check the parameters */
  assert_param(IS_RTC_BKP(BackupRegister));

  tmp = (uint32_t)BKP_BASE;
  tmp += (BackupRegister * 4U);

  *(__IO uint32_t *) tmp = (Data & BKP_DR1_D);
}

/**
  * @brief  Reads data from the specified RTC Backup data Register.
  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
  *                the configuration information for RTC.
  * @param  BackupRegister: RTC Backup data Register number.
  *          This parameter can be: RTC_BKP_DRx where x can be from 1 to 10 (or 42) to
  *                                 specify the register (depending devices).
  * @retval Read value
  */
uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
{
  uint32_t backupregister = 0U;
  uint32_t pvalue = 0U;

  /* Prevent unused argument(s) compilation warning */
  UNUSED(hrtc);

  /* Check the parameters */
  assert_param(IS_RTC_BKP(BackupRegister));

  backupregister = (uint32_t)BKP_BASE;
  backupregister += (BackupRegister * 4U);

  pvalue = (*(__IO uint32_t *)(backupregister)) & BKP_DR1_D;

  /* Read the specified register */
  return pvalue;
}

 

F103의 경우 10개가 있나 보다. 그런데 BKP_DRn_D 마스크는 왜 전부 0xFFFF 으로 동일한걸까?

stm32f103xb.h

/******************************************************************************/
/*                                                                            */
/*                            Backup registers                                */
/*                                                                            */
/******************************************************************************/

/*******************  Bit definition for BKP_DR1 register  ********************/
#define BKP_DR1_D_Pos                       (0U)                               
#define BKP_DR1_D_Msk                       (0xFFFFUL << BKP_DR1_D_Pos)         /*!< 0x0000FFFF */
#define BKP_DR1_D                           BKP_DR1_D_Msk                      /*!< Backup data */

/*******************  Bit definition for BKP_DR2 register  ********************/
#define BKP_DR2_D_Pos                       (0U)                               
#define BKP_DR2_D_Msk                       (0xFFFFUL << BKP_DR2_D_Pos)         /*!< 0x0000FFFF */
#define BKP_DR2_D                           BKP_DR2_D_Msk                      /*!< Backup data */

/*******************  Bit definition for BKP_DR3 register  ********************/
#define BKP_DR3_D_Pos                       (0U)                               
#define BKP_DR3_D_Msk                       (0xFFFFUL << BKP_DR3_D_Pos)         /*!< 0x0000FFFF */
#define BKP_DR3_D                           BKP_DR3_D_Msk                      /*!< Backup data */

/*******************  Bit definition for BKP_DR4 register  ********************/
#define BKP_DR4_D_Pos                       (0U)                               
#define BKP_DR4_D_Msk                       (0xFFFFUL << BKP_DR4_D_Pos)         /*!< 0x0000FFFF */
#define BKP_DR4_D                           BKP_DR4_D_Msk                      /*!< Backup data */

/*******************  Bit definition for BKP_DR5 register  ********************/
#define BKP_DR5_D_Pos                       (0U)                               
#define BKP_DR5_D_Msk                       (0xFFFFUL << BKP_DR5_D_Pos)         /*!< 0x0000FFFF */
#define BKP_DR5_D                           BKP_DR5_D_Msk                      /*!< Backup data */

/*******************  Bit definition for BKP_DR6 register  ********************/
#define BKP_DR6_D_Pos                       (0U)                               
#define BKP_DR6_D_Msk                       (0xFFFFUL << BKP_DR6_D_Pos)         /*!< 0x0000FFFF */
#define BKP_DR6_D                           BKP_DR6_D_Msk                      /*!< Backup data */

/*******************  Bit definition for BKP_DR7 register  ********************/
#define BKP_DR7_D_Pos                       (0U)                               
#define BKP_DR7_D_Msk                       (0xFFFFUL << BKP_DR7_D_Pos)         /*!< 0x0000FFFF */
#define BKP_DR7_D                           BKP_DR7_D_Msk                      /*!< Backup data */

/*******************  Bit definition for BKP_DR8 register  ********************/
#define BKP_DR8_D_Pos                       (0U)                               
#define BKP_DR8_D_Msk                       (0xFFFFUL << BKP_DR8_D_Pos)         /*!< 0x0000FFFF */
#define BKP_DR8_D                           BKP_DR8_D_Msk                      /*!< Backup data */

/*******************  Bit definition for BKP_DR9 register  ********************/
#define BKP_DR9_D_Pos                       (0U)                               
#define BKP_DR9_D_Msk                       (0xFFFFUL << BKP_DR9_D_Pos)         /*!< 0x0000FFFF */
#define BKP_DR9_D                           BKP_DR9_D_Msk                      /*!< Backup data */

/*******************  Bit definition for BKP_DR10 register  *******************/
#define BKP_DR10_D_Pos                      (0U)                               
#define BKP_DR10_D_Msk                      (0xFFFFUL << BKP_DR10_D_Pos)        /*!< 0x0000FFFF */
#define BKP_DR10_D                          BKP_DR10_D_Msk                     /*!< Backup data */

#define RTC_BKP_NUMBER 10

 

[링크 : https://fuhehe.tistory.com/27]

 

1.9 Backup registers
RTC_BKPxR, where x=0 to n backup registers (80 bytes), are reset when a tamper detection event occurs. These registers are powered-on by VBAT when VDD is switched off, so that they are not reset by a system reset, and their contents remain valid when the device operates in low-power mode.
Note: The number “n” of backup registers depends on the product. Please refer to Table 15: Advanced RTC features.

[링크 : https://www.st.com/resource/en/application_note/an3371-using-the-hardware-realtime-clock-rtc-in-stm32-f0-f2-f3-f4-and-l1-series-of-mcus-stmicroelectronics.pdf]

 

보안상 문제가 발생하면 그걸 TAMP 라는것 같은데, 아무튼 그 때는 백업 레지스터가 초기화 된다고 한다.

 

[링크 : https://www.st.com/resource/en/product_training/STM32MP1-Security-Tamper_TAMP.pdf]

'embeded > Cortex-M3 STM' 카테고리의 다른 글

stm32f103c8t6 cpp std::cout 실패  (0) 2026.02.18
stm32 rtc tamper  (0) 2026.01.29
stm32 hal rcc flag  (0) 2026.01.27
stm32 ivt  (0) 2026.01.27
bluepill stm32f103c8t6 USB CDC 리셋이후 안되는 문제  (0) 2026.01.27
Posted by 구차니
embeded/Cortex-M3 STM2026. 1. 27. 18:26

대충 보니

BOR Reset(brown out detection reset - 전압 강하로 인한 재기동)

PIN Reset (NRST pin reset - 하드웨어 리셋)

POR Reset (Power on Reset)

SFT Reset (Software Reset)

IWDG1 Reset (Independent Watchdog reset)

WWDG Reset (window Watchdog reset)

#define RCC_FLAG_BORRST                ((uint8_t)0x95)
#define RCC_FLAG_PINRST                ((uint8_t)0x96)
#define RCC_FLAG_PORRST                ((uint8_t)0x97)
#define RCC_FLAG_SFTRST                ((uint8_t)0x98)
#define RCC_FLAG_IWDG1RST              ((uint8_t)0x9A)
#define RCC_FLAG_WWDG1RST              ((uint8_t)0x9C)
#define RCC_FLAG_LPWR1RST              ((uint8_t)0x9E)
#define RCC_FLAG_LPWR2RST              ((uint8_t)0x9F)

[링크 : https://community.st.com/t5/stm32-mcus-products/software-reset-flag-sftrstf-in-rcc-csr-register-what-source/td-p/544463]

[링크 : https://community.st.com/t5/stm32-mcus-products/stm32f407-spurious-reset-rcc-flag-pinrst/td-p/147931]

 

저전력 모드 보안 리셋은 멀까?

3.7.2 System reset sources
Power-on reset initializes all registers while system reset reinitializes the system except for
the debug, part of the RCC and power controller status registers, as well as the backup
power domain.
A system reset is generated in the following cases:
• Power-on reset (pwr_por_rst)
• Brownout reset
• Low level on NRST pin (external reset)
• Independent watchdog 1 (from D1 domain)
• Independent watchdog 2 (from D2 domain)
• Window watchdog 1 (from D1 domain)
• Window watchdog 2 (from D2 domain)
• Software reset
• Low-power mode security reset
• Exit from Standby

[링크 :https://www.st.com/resource/en/datasheet/stm32h757ai.pdf]

 

stop / standby mode 오갈때 뜨는 듯?

A low-power-mode security reset (which is generated when Stop or Standby mode is entered but is prohibited by the option byte configuration)

[링크 : https://www.st.com/content/ccc/resource/training/technical/product_training/group0/81/96/f3/1a/55/d9/40/52/STM32H7-System-Reset_and_clock_control_RCC/files/STM32H7-System-Reset_and_clock_control_RCC.pdf/_jcr_content/translations/en.STM32H7-System-Reset_and_clock_control_RCC.pdf]

 

'embeded > Cortex-M3 STM' 카테고리의 다른 글

stm32 rtc tamper  (0) 2026.01.29
stm32f103 rtc backup register  (0) 2026.01.29
stm32 ivt  (0) 2026.01.27
bluepill stm32f103c8t6 USB CDC 리셋이후 안되는 문제  (0) 2026.01.27
stm32cubeide 2.0 에서 ioc 파일이 생성 안되네?  (0) 2026.01.11
Posted by 구차니