ART/MIF 를 통해서 NVM Bank 1 / 2에 접근하는거라면.. ART를 그럼 사실상 강제하게 되는건가?
서로 다른 채널에 read / write 를 동시에 할 수 있다가 dual bank 의 장점인가?
The dual bank memory can be configured and used as a single large NVM block with continuous addressing (with few exceptions, not covered in this document). There are significant advantages when the NVM is configured to serve as two parallel blocks, the most important is the possibility to write on one bank without interrupting reading (and fetching instructions) from the other bank. This is the most important prerequisite to perform the updates without breaking the execution of the code from the program NVM.
Core: Arm®32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from flash memory, frequency up to 180 MHz, MPU, 225 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
Memories
512 bytes of OTP memory
Up to 2 MB of flash memory organized into two banks allowing read-while-write
Up to 256+4 KB of SRAM including 64 KB of CCM (core coupled memory) data RAM
Flexible external memory controller with up to 32-bit data bus: SRAM, PSRAM, SDRAM/LPSDR SDRAM, compact flash/NOR/NAND memories
LCD parallel interface, 8080/6800 modes
LCD-TFT controller with fully programmable resolution (total width up to 4096 pixels, total height up to 2048 lines and pixel clock up to 83 MHz)
Chrom-ART Accelerator™ for enhanced graphic content creation (DMA2D)