구차니의 잡동사니 모음

10. Click SOF Data, and select Add File, and select your .sof file

11. Click Add Hex data, select Relative addressing, and select your .hex file created above

12. Now push generate. You should verify that the generated .map file has Page_0 at a start address of 0x0, and the hex file at a start address 1 after the end address of Page_0

13. Now in the Quartus II Programmer, select Add File and select your .jic file. Check the Program box next to the .jic file, and push Start

Creating the .jic file:

In Quartus, open the Convert "Programming File..." utility

Set the "Programming file type:" to "JTAG Indirect Configuration File (.jic)"

In "Input files to convert" select "Flash Loader", click "Add Device..." and choose your target FPGA device

If you are configuring the FPGA from the serial flash:

In "Input files to convert" select "SOF Data", click "Add File..." and select your FPGA .sof file

-With "SOF Data" selected, click "Properties", in the "SOF Data Properies dialogue box:

-Set "Address mode for selected pages to" to "Start"

Set "Start address (32-bit hexidecimal:) to 0x0.

In "Input files to convert" click "Add Hex Data", in the "Add Hex Data" dialogue box:

Set "Addressing mode" to "Absolute addressing"

Select your hex file using the "..." button next to the "Hex file" field

Click "OK"

Check "Create Memory Map File". This is useful for debugging.

Generate the .jic file and program it into the serial flash with the Quartus Programmer 

13:50:21 **** Build of configuration Nios II for project hello_world_0 ****

make mem_init_generate 

Info: Building ../hello_world_0_bsp/

C:/intelFPGA_lite/17.1/nios2eds/bin/gnu/H-x86_64-mingw32/bin/make --no-print-directory -C ../hello_world_0_bsp/

[BSP build complete]

Post-processing to create mem_init/hdl_sim/unsaved_epcs_flash_controller_0_boot_rom.hex...

elf2hex hello_world_0.elf 0x00011000 0x000117ff --width=32 --little-endian-mem --create-lanes=0 --no-zero-fill mem_init/hdl_sim/unsaved_epcs_flash_controller_0_boot_rom.hex

Post-processing to create mem_init/unsaved_onchip_memory2_0.hex...

elf2hex hello_world_0.elf 0x00008000 0x0000ffff --width=32 --little-endian-mem --create-lanes=0 mem_init/unsaved_onchip_memory2_0.hex

Post-processing to create mem_init/hdl_sim/unsaved_epcs_flash_controller_0_boot_rom.dat...

elf2dat --infile=hello_world_0.elf --outfile=mem_init/hdl_sim/unsaved_epcs_flash_controller_0_boot_rom.dat \

--base=0x00011000 --end=0x000117ff --width=32 \

--little-endian-mem --create-lanes=0 

Post-processing to create mem_init/hdl_sim/unsaved_onchip_memory2_0.dat...

elf2dat --infile=hello_world_0.elf --outfile=mem_init/hdl_sim/unsaved_onchip_memory2_0.dat \

--base=0x00008000 --end=0x0000ffff --width=32 \

--little-endian-mem --create-lanes=0 

Post-processing to create mem_init/hdl_sim/unsaved_epcs_flash_controller_0_boot_rom.sym...

nios2-elf-nm -n hello_world_0.elf > mem_init/hdl_sim/unsaved_epcs_flash_controller_0_boot_rom.sym

Post-processing to create mem_init/hdl_sim/unsaved_onchip_memory2_0.sym...

nios2-elf-nm -n hello_world_0.elf > mem_init/hdl_sim/unsaved_onchip_memory2_0.sym

Post-processing to create unsaved_epcs_flash_controller_0_boot_rom.flash...

elf2flash --input=hello_world_0.elf --outfile=unsaved_epcs_flash_controller_0_boot_rom.flash --sim_optimize=0 --little-endian-mem \

 --epcs 

Post-processing to create mem_init/meminit.spd...

Post-processing to create mem_init/meminit.qip...

13:50:26 Build Finished (took 4s.961ms) 

3.3.1.3 EPCS Parameters

3.3.2 Programming Both Hardware and Software into an EPCS/EPCQ

Device

The --base parameter is not available for EPCS/EPCQ devices, because in EPCS/EPCQ devices, FPGA configuration data must start at address 0x0. However, if you are programming both an FPGA configuration and a Nios II software executable in the EPCS/EPCQ device, the --after parameter lets you position the software executable directly after the FPGA configuration data.

Convert the FPGA configuration file first using sof2flash. When converting the Nios II software executable, use the --after parameter, and specify the FPGA configuration S-record file. The S-record output for the software executable starts at the first address unused by the FPGA configuration. Refer to the second example under the “elf2flash Command-Line Examples” chapter.

Note: elf2flash does not insert the FPGA configuration into the output file. It simply leaves space, starting at offset 0x0, that is large enough for the configuration data.

Note: In Intel Quartus Prime software version 13.1 and onwards, the -epcs/--epcq option in sof2flash generates .flash file with a SOF header, which contains the SOF length.

This change is required for V-series devices and above for new SOF format, and to allow for future SOF format variations. The Nios II bootcopier loads the Nios II software executable from EPCS/EPCQ devices based on the SOF length. For more information about how to program EPCS/EPCQ devices, refer to the "KDB Solution rd11192013_118" webpage.

Related Links

• elf2flash Command-Line Examples on page 25

• KDB Solution rd11192013_118 

13:01:21 **** Incremental Build of configuration Nios II for project hello_world_0_bsp ****

make all 

Makefile not up to date.

../../unsaved.sopcinfo has been modified since the BSP was generated.

Generate the BSP to update the Makefile, and then build again.

To generate from Eclipse:

 1. Right-click the BSP project.

 2. In the Nios II Menu, click Generate BSP.

To generate from the command line:

 nios2-bsp-generate-files --settings=<settings file> --bsp-dir=<target bsp files directory>

make: *** [public.mk] Error 1

13:01:22 Build Finished (took 946ms)

• A Dhrystone 2.1 performance rating of 0.252 DMIPS/MHz yields an unmatched 26.85 times speed up over the original 80C51 chip operating at the same frequency.
• Maximum CPU frequency exceeds 500 MHz for a class-leading effective increase of more than 1,000 times over 80C51 chips (40nm G process) 

EPCS Controller-Based Boot Copier

EPCS controller-based boot copier supports EPCS memory only. Boot copier is stored in the ROM within

the EPCS flash controller. The boot copier is included during Qsys and Quartus Prime project compila‐

tion time.

The next stage boot image is located in the EPCS memory flash. The EPCS controller-based boot copier is

automatically appended into the SREC image (*.flash) file during the elf2flash utility execution in the

Nios II Flash Programming flow method.

EPCS Controller-Based Boot Copier

EPCS controller-based boot copier supports EPCS memory only. Boot copier is stored in the ROM within

the EPCS flash controller. The boot copier is included during Qsys and Quartus Prime project compila‐

tion time.

The next stage boot image is located in the EPCS memory flash. The EPCS controller-based boot copier is

automatically appended into the SREC image (*.flash) file during the elf2flash utility execution in the

Nios II Flash Programming flow method. 

My application contains:

1. Clock Source

2. Nios II Processor

3. System ID

4. JTAG UART

5. EPCS Serial Flash Controller

6. PIO

7. SDRAM Controller

Make sure the Nios II’s Reset Vector is pointing at EPCS/EPCQ Controller. 

Nios II Gen2 Processor Feature Enhancements

The Nios II Gen2 processor family consists of /e and /f cores. It offers improvements over the Nios II Classic processor cores:

• Optional full 32-bit address space 

• Optional user-defined Peripheral address region for data cache bypass 

• Improved Qsys interface

The Nios II Gen2 /e core is completely backwards compatible with the Nios II Classic /s core. The Nios II Classic /s core has no direct equivalent in the Nios II Gen 2 family, however the Nios II Gen2 /f processor (as it has a more flexible configuration capability) can be configured to have the same feature set as the Nios II Classic /s core.

The Nios II Gen2 /f core offers the following feature enhancements over the Nios II Classic /f core: 

• Optional full ECC support, including data cache and TCMs (Tightly-coupled Memories) 

• Optional static branch prediction 

• Higher performance multiplier

• Improved and more deterministic divider 

• 64-bit multiply supported on all devices 

• Improved low-cost shifter implementation up to 4 bits/cycle 

• Instruction cache is now optional even when JTAG debug is present 

• New system interface for system trace