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Revision Name fpgaminer

Top-level Entity Name fpgaminer_top

Family Cyclone IV E

Device EP4CE22F17C6

Timing Models Final

Total logic elements 17,503 / 22,320 ( 78 % )

Total registers 11388

Total pins 19 / 154 ( 12 % )

Total virtual pins 0

Total memory bits 5,696 / 608,256 ( < 1 % )

Embedded Multiplier 9-bit elements 0 / 132 ( 0 % )

Total PLLs 1 / 4 ( 25 % )

D-SUN "USB to TTL" (Blue)

(Rx & Tx use 3.3V logic levels) 

Gikfun YP-02 USB to TTL, CH340, 6-pin

(Rx & Tx use ~3.7V logic levels) 

defparam

// NB Uncomment BOTH divide, multiply and frequency settings according to osc speed

// Also change clock period in fpgaminer.sdc

// -------------------------------------------------------------------------------

// altpll_component.clk0_divide_by = 1, // 5 MHz osc

// altpll_component.clk0_divide_by = 1, // 10MHz osc

altpll_component.clk0_divide_by = 2, // 20MHz osc [IN USE]

altpll_component.clk0_duty_cycle = 50,

// altpll_component.clk0_multiply_by = `SPEED_MHZ * 2, // 5MHz osc

// altpll_component.clk0_multiply_by = `SPEED_MHZ, // 10MHz osc

altpll_component.clk0_multiply_by = `SPEED_MHZ, // 20MHz osc  [IN USE]

altpll_component.clk0_phase_shift = "0",

altpll_component.compensate_clock = "CLK0",

// NB inclk0_input_frequency is actually the clock PERIOD in picoseconds 

// altpll_component.inclk0_input_frequency = 200000, // 5 MHz osc

// altpll_component.inclk0_input_frequency = 100000, // 10 MHz osc

altpll_component.inclk0_input_frequency = 50000, // 20 MHz osc [IN USE]

altpll_component.intended_device_family = "Cyclone IV E", 

The PLL clock speed is set by the parameter (Verilog macro) SPEED_MHZ in units of 10MHz,

eg SPEED_MHZ=4 runs at 40MHz, which is the default setting. This gives 6.67MHash/s

throughput. This is the fastest that I recommend running an unmodified DE0-Nano. You may

clock faster at your own risk, but you should monitor the temperature of the the onboard

regulator chips as these will get VERY hot unless additional cooling is applied (eg fan

blown air). The fpga chip may also need cooling. BEWARE, you risk destroying your board

due to overheating if you increase SPEED_MHZ, and the actual speed in MHz is 10 times the

value set for SPEED_MHZ.

Current draw is approx 10mA per MHz (eg 40MHz will draw approx 400mA). Beware that a

typical USB port may only be able to supply 500mA so a 5.0 Volt external power supply

connected to the DE0-Nano white PSU header (JP4) is advised if overclocking. I have not

myself run this configuration any faster than 80MHz (SPEED_MHZ=8), and fan cooling was

essential.

After programming, the miner starts up in a halted state (it does NOT mine in this state)

Pressing the KEY0 pushbutton on the DE0-Nano board will start the miner (and reset the

nonce). Pressing KEY1 will halt it. This allows some control of power and thermal

management as the halted state draws considerably less current from the power supply.

This was of importance when extreme overclocking was applied to the Hashers22_serial

version as follows. 

You will then be prompted to select a SOF to program, best to start with DE0_Nano_serial-40MHz.sof

Programming should only take a second or two. The blinkenlights demo should now change to a simple binary

count. This is the top byte of the nonce and gives a good indication of the hash speed (its 2^32 divided

by the time in seconds for a complete cycle, or roughly one increment per second translates to 16.78MH/s). 

 [DRC UCIO-1] Unconstrained Logical Port: 57 out of 71 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.  Problem ports: wbInputData[29], wbInputData[28], wbInputData[27], wbInputData[25], wbInputData[24], wbInputData[23], wbInputData[21], wbInputData[20], wbInputData[18], wbInputData[17], wbInputData[16], wbInputData[15], wbInputData[14], wbInputData[13], wbInputData[12]... and (the first 15 of 57 listed).

#define UART_ENABLE_UPDATE

#define UART_AUTOBAUD

//#define UART_FIXED_BAUDRATE     115200

#define UART_CLOCK_ENABLE         SYSCTL_RCGCUART_R0

#define UARTx_BASE                UART0_BASE

#define UART_RXPIN_CLOCK_ENABLE   SYSCTL_RCGCGPIO_R0

#define UART_RXPIN_BASE         GPIO_PORTA_BASE

#define UART_RXPIN_PCTL         0x1

#define UART_RXPIN_POS          0

#define UART_TXPIN_CLOCK_ENABLE SYSCTL_RCGCGPIO_R0

#define UART_TXPIN_BASE         GPIO_PORTA_BASE

#define UART_TXPIN_PCTL         0x1

#define UART_TXPIN_POS          1

#define UART_ENABLE_UPDATE

//#define UART_AUTOBAUD

#define UART_FIXED_BAUDRATE     38400

#define UART_CLOCK_ENABLE         SYSCTL_RCGCUART_R1

#define UARTx_BASE                UART1_BASE

#define UART_RXPIN_CLOCK_ENABLE   SYSCTL_RCGCGPIO_R1

#define UART_RXPIN_BASE         GPIO_PORTB_BASE

#define UART_RXPIN_PCTL         0x1

#define UART_RXPIN_POS          0

#define UART_TXPIN_CLOCK_ENABLE SYSCTL_RCGCGPIO_R1

#define UART_TXPIN_BASE         GPIO_PORTB_BASE

#define UART_TXPIN_PCTL         0x1

#define UART_TXPIN_POS          1

void

UARTSend(const uint8_t *pui8Data, uint32_t ui32Size)

{

    //

    // Transmit the number of bytes requested on the UART port.

    //

    GPIOPinWrite(GPIO_PORTB_BASE, GPIO_PIN_2, GPIO_PIN_2);

    Delay(10);

    while(ui32Size--)

    {

        //

        // Make sure that the transmit FIFO is not full.

        //

        while((HWREG(UARTx_BASE + UART_O_FR) & UART_FR_TXFF))

        {

        }

        //

        // Send out the next byte.

        //

        HWREG(UARTx_BASE + UART_O_DR) = *pui8Data++;

    }

    //

    // Wait until the UART is done transmitting.

    //

    UARTFlush();

    GPIOPinWrite(GPIO_PORTB_BASE, GPIO_PIN_2, 0);

    Delay(10);

} 

LR_IROM 0x00001000 0x00040000

{

    ER_IROM 0x00001000 0x00040000

    {

        *.o (RESET, +First)

        * (InRoot$$Sections, +RO)

    }

    RW_IRAM 0x20000000 0x00008000

    {

        ;* (vtable, +First)

        * (+RW, +ZI)

    }

} 

To program a device in JTAG or Passive Serial mode: