구차니의 잡동사니 모음

C:\intelFPGA_lite\17.1\nios2eds\bin

C:\intelFPGA_lite\17.1\nios2eds\bin\gnu\H-x86_64-mingw32\bin 

D:\>C:\intelFPGA_lite\17.1\nios2eds\bin\elf2flash.exe --input=hello_world_0.elf --output=swimage.flash --epcs

D:\>dir

2018-01-27  오후 01:19               946 hello_world.c

2018-01-27  오후 01:20           319,239 hello_world_0.elf

2018-01-27  오후 01:20            86,021 hello_world_0.map

2018-01-29  오후 01:53            11,824 swimage.flash

D:\>C:\intelFPGA_lite\17.1\nios2eds\bin\gnu\H-x86_64-mingw32\bin\nios2-elf-objcopy.exe -I srec -O ihex swimage.flash  swimage.hex

D:\>dir

2018-01-27  오후 01:19               946 hello_world.c

2018-01-27  오후 01:20           319,239 hello_world_0.elf

2018-01-27  오후 01:20            86,021 hello_world_0.map

2018-01-29  오후 01:53            11,824 swimage.flash

2018-01-29  오후 01:57            13,272 swimage.hex 

S00600002D454C3B

S325000000007C0F00000000010074004000140840083A6800080000000000000000000000008C

S3250000002000000000000000007400C0061400E0DE74008006148CA4D67400800014498510B4

S325000000407400C000144DC5182603C010150000100401801036FDFF10C0251000C03310003B

:100000007C0F00000000010074004000140840084C

:100010003A68000800000000000000000000000036

:1000200000000000000000007400C0061400E0DEC4

:1000300074008006148CA4D67400800014498510C6

sof2flash --input=<hwimage>.sof --output=hwimage.flash --epcs --verbose

elf2flash --input=<elf file>.elf --output=swimage.flash --epcs --after=hwimage.flash --verbose

nios2-elf-objcopy -I srec -O ihex hwimage.flash  hwimage.hex

nios2-elf-objcopy -I srec -O ihex swimage.flash  swimage.hex 

The method used to create a .jic file with a Nios® II hardware and software image is as follows.

1. Create a flash file from a .sof file: sof2flash --input=<hwimage>.sof --output=hwimage.flash --epcs --verbose

2. Create a flash file from a ,elf file: elf2flash --input=<elf file>.elf --output=swimage.flash --epcs --after=hwimage.flash --verbose

3. Convert the .flash image into a.hex file: nios2-elf-objcopy --input-target srec --output-target ihex mysw.flash mysw.hex

4. In the Quartus® II software, open File > Convert Programming Files > Set the programming file as JTAG Indirect Configuration File (.jic).

6. Select the correct size EPCS device in the Configuration pull-down

7. Name your output .jic file

8. Click Flash Loader below, and select Add Device on the right hand side

9. Select your FPGA device from the list

10. Click SOF Data, and select Add File, and select your .sof file

11. Click Add Hex data, select Relative addressing, and select your .hex file created above

12. Now push generate. You should verify that the generated .map file has Page_0 at a start address of 0x0, and the hex file at a start address 1 after the end address of Page_0

13. Now in the Quartus II Programmer, select Add File and select your .jic file. Check the Program box next to the .jic file, and push Start 

The method used to create a .jic file with a Nios® II hardware and software image is as follows.

1.      Create a flash file for the hardware and software image
sof2flash --input=<hwimage>.sof --output=hwimage.flash --epcs --verbose
elf2flash --input=<elf file>.elf --output=swimage.flash --epcs --after=hwimage.flash --verbose

Note: When creating the software flash image, there is no need to add a boot srec (this is located in the EPCS Controller), the --after option ensures the software image starts immediately after the hardware image.

2.      Convert the flash images into Hex files

nios2-elf-objcopy -I srec -O ihex hwimage.flash  hwimage.hex
nios2-elf-objcopy -I srec -O ihex swimage.flash  swimage.hex

3.      When creating your jic file using Quartus® II Convert Programming File tool, add the Flash Loader and both hex files with absolute addressing option selected.

Note: You do not need to add the .sof file to the jic image.  This is because you created a hardware hex image.  Using the hardware hex image ensures the software hex image is at the proper offset in the EPCS. 

nios2-elf-g++  -T'../hello_world_0_bsp//linker.x' -msys-crt0='../hello_world_0_bsp//obj/HAL/src/crt0.o' -msys-lib=hal_bsp -L../hello_world_0_bsp/   -Wl,-Map=hello_world_0.map   -O0 -g -Wall   -mno-hw-div -mno-hw-mul -mno-hw-mulx -mgpopt=global  -o hello_world_0.elf obj/default/hello_world.o -lm -msys-lib=m

c:/intelfpga_lite/17.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/bin/ld.exe: address 0x18dc0 of hello_world_0.elf section `.bss' is not within region `onchip_memory2_0'

c:/intelfpga_lite/17.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/5.3.0/../../../../../H-x86_64-mingw32/nios2-elf/bin/ld.exe: address 0x18dc0 of hello_world_0.elf section `.bss' is not within region `onchip_memory2_0'

collect2.exe: error: ld returned 1 exit status

make: *** [hello_world_0.elf] Error 1

/*

 * "Hello World" example.

 *

 * This example prints 'Hello from Nios II' to the STDOUT stream. It runs on

 * the Nios II 'standard', 'full_featured', 'fast', and 'low_cost' example

 * designs. It runs with or without the MicroC/OS-II RTOS and requires a STDOUT

 * device in your system's hardware.

 * The memory footprint of this hosted application is ~69 kbytes by default

 * using the standard reference design.

 *

 * For a reduced footprint version of this template, and an explanation of how

 * to reduce the memory footprint for a given application, see the

 * "small_hello_world" template.

 *

 */

#include <stdio.h>

#include "system.h"

#include "altera_avalon_pio_regs.h"

int main() {

printf("Hello from Nios II!\n");

int count = 0;

int delay;

while (1) {

IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, count & 0x01);

delay = 0;

while (delay < 1000000) {

delay++;

}

count++;

}

return 0;

} 

STM32F4:            902,       gcc-arm

AVR90USB1286:  237,       gcc-avr 

 Raspberry Pi           Linux                   

  ARM  1176      700     3.6.11      847          

  ARM  1176     1000     3.6.11     1226          

  Raspberry Pi 2                                  

  ARM V7A       900      3.18.5     1538          

  ARM v7A      1000      3.18.5     1694          

 gcc 4.8                                        

  ARM V7A       900      3.18.5     1667          

  ARM V7A      1000      3.18.5     1852          

  Raspberry Pi 3, 32 Bit                          

  ARM v8-A53   1200      4.1.19     2201          

  gcc 4.8                                         

  ARM v8-A53   1200      4.1.19     2469          

  Raspberry Pi 3, 64 Bit                          

  OpenSuse                                        

  ARM v8-A53   1200      4.4.36     3536          

  Gentoo                                          

  ARM v8-A53   1200      4.10.0     3475           

module unsaved (

input  wire       clk_clk,                          //                       clk.clk

output wire [7:0] pio_0_external_connection_export, // pio_0_external_connection.export

input  wire       reset_reset_n                     //                     reset.reset_n

);

//=======================================================

//  Structural coding

//=======================================================

unsaved nios2_inst(.clk_clk (CLOCK_50), .pio_0_external_connection_export(LED), .reset_reset_n(1'b1)); 

Error (170040): Can't place all RAM cells in design

Info (170034): Selected device has 66 memory locations of type M9K. The current design requires 69 memory locations of type M9K to successfully fit.

Info (170033): Memory usage required for the design in the current device: 105% M9K memory block locations required

Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00

Info (11888): Total time spent on timing analysis during the Fitter is 0.04 seconds.

Error (171000): Can't fit design in device

unsaved nios2_inst0(.clk_clk (CLOCK_50), .pio_0_external_connection_export(LED), .reset_reset_n(1'b1));

unsaved nios2_inst1(.clk_clk (CLOCK_50), .reset_reset_n(1'b1));

unsaved nios2_inst2(.clk_clk (CLOCK_50), .reset_reset_n(1'b1));

unsaved nios2_inst3(.clk_clk (CLOCK_50), .reset_reset_n(1'b1)); 

Error (170048): Selected device has 66 RAM location(s) of type M9K.  However, the current design needs more than 66 to successfully fit

Info (170057): List of RAM cells constrained to M9K locations

Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00

Info (11888): Total time spent on timing analysis during the Fitter is 0.17 seconds.

Error (171000): Can't fit design in device

The original plan was the smaller Artix would not have the AES/HMAC and XADC blocks.

This was changed pretty recently - now all 7 series devices will be uniform in the support of these features. 

Encryption, Readback, and Partial Reconfiguration

In all 7 series FPGAs (except XC7S6 and XC7S15), the FPGA bitstream, which contains sensitive customer IP, can be protected with 256-bit AES encryption and HMAC/SHA-256 authentication to prevent unauthorized copying of the design. The FPGA performs decryption on the fly during configuration using an internally stored 256-bit key. This key can reside in battery-backed RAM or in nonvolatile eFUSE bits. Most configuration data can be read back without affecting the system's operation. Typically, configuration is an all-or-nothing operation, but Xilinx 7 series FPGAs support partial reconfiguration. This is an extremely powerful and flexible feature that allows the user to change portions of the FPGA while other portions remain static. Users can time-slice these portions to fit more IP into smaller devices, saving cost and power. Where applicable in certain designs, partial reconfiguration can greatly improve the versatility of the FPGA.