구차니의 잡동사니 모음

`timescale 1ns/100ps

module Counter_tb;

reg        clk;

reg        rst_n;

wire [7:0] cnt;

// 20 ns 이다..

parameter PERIOD = 20; 

Counter counter (

  .CLK(clk),

  .RST_N(rst_n),

  .CNT(cnt)

);

initial begin

  #0  clk   = 1'b0;

      rst_n = 1'b0;

  #10 rst_n = 1'b1;

end

// 50MHz 코멘트를 잘달자

always #(PERIOD/2) clk = ~clk;

endmodule 

How do I generate clock in Verilog ?

There are many ways to generate clock in Verilog; you could use one of the following methods:

Method #1

 1 initial begin

 2  clk = 0;

 3 end

 4    

 5 always begin

 6    #5  clk = ~clk;

 7 

 8 end

You could download file clock_always.v here

Method #2

 1 initial begin

 2   clk = 0;

 3   forever begin

 4      #5  clk = ~clk;

 5   end

 6 end

You could download file clock_forever.v here

Method #3

 1 initial begin

 2   clk = 0;

 3 end

 4 

 5 always begin

 6    #5  clk = 0;

 7    #5  clk = 1;

 8 end 

FpgaOriginal.zipを展開するには，パスワードが必要です．

パスワードは，

 第1部 1日目 図1-23のタイトルにある8ケタの数字

 第2部 15日目 図15-15のタイトルにある5文字のアルファベット

 Appendix A 図A-4のタイトルにある7文字のアルファベット

以上をハイフンでつないだ文字列です．

例：12345678-YYYYY-ZZZZZZZ

すべて半角文字，アルファベットは大文字小文字に注意してください． 

Archiving Projects

You can save the elements of a project in a single, compressed Quartus II Archive File (. qar) by clicking

Project > Archive Project.

The .qar captures logic design, project, and settings files required to restore the project.

Use this technique to share projects between designers, or to transfer your project to a new version of the

Quartus II software, or to Altera support. You can optionally add compilation results, Qsys system files, and

third-party EDA tool files to the archive. If you restore the archive in a different version of the Quartus II

software, you must include the original .qdf in the archive to preserve original compilation results.

게이트-레벨시뮬레이션은타이밍시뮬레이션에서 기능적결과의차이만을확인한다. 만약게이트-레벨시뮬레 이션은문제없고타이밍시뮬레이션이실패했다면, 넷리스트 가아닌타이밍으로발생된부분임을나타낸다. 백-어노테이트 타이밍 시뮬레이션은 타이밍 정보가 있는 게이트-레벨 시뮬레이션이다. 이를 위해 FPGA 벤더는 VITAL (VHDL Gate Level) 넷리스트 또는 Verilog 넷리스 트를 생성한다 

 always @ (posedge clk or negedge rst)

begin

if (~rst)

cnt <= 0;

else

begin

if(cnt < 834000)

cnt <= cnt + 1;

else

cnt <= 0;

end

if(cnt < HSYNC)

hsync <= 1;

else hsync <= 0;

if(cnt < VSYNC)

vsync <= 1;

else vsync <= 0;

end

 always @ (posedge clk or negedge rst)

begin

if (~rst)

cnt <= 0;

else

begin

if(cnt < 834000)

begin

cnt <= cnt + 1;

if(cnt < HSYNC)

hsync <= 1;

else hsync <= 0;

if(cnt < VSYNC)

vsync <= 1;

else vsync <= 0;

end

else

cnt <= 0;

end

end

//=======================================================

//  This code is generated by Terasic System Builder

//=======================================================

module PwmCtrl(RST_N, CLK, LED0);

input RST_N, CLK;

output LED0;

reg[27:0] counter0;

always @(negedge RST_N or posedge CLK)

begin

if(RST_N == 1'b0)

begin

counter0 <= 0;

end else begin

counter0 <= counter0 + 1;

end

end

assign LED0 = counter0[26];

endmodule

module DE0_NANO(

//////////// CLOCK //////////

CLOCK_50,

//////////// LED //////////

LED,

//////////// KEY //////////

KEY 

);

//=======================================================

//  PARAMETER declarations

//=======================================================

//=======================================================

//  PORT declarations

//=======================================================

//////////// CLOCK //////////

input           CLOCK_50;

//////////// LED //////////

output      [7:0] LED;

//////////// KEY //////////

input      [1:0] KEY;

//=======================================================

//  REG/WIRE declarations

//=======================================================

//=======================================================

//  Structural coding

//=======================================================

PwmCtrl pwm(KEY[0],

CLOCK_50,

LED[0]);

endmodule