17년 이후로 Nios ii gen 2로 바뀌면서 nios ii/s는 사라지고 f만 남은거 같은데
그러면 위에 ip-nios랑 ipr-nios는 f인가? 머지?
Nios II classic is offered in 3 different configurations: Nios II/f (fast), Nios II/s (standard), and Nios II/e (economy). Nios II gen2 is offered in 2 different configurations: Nios II/f (fast), and Nios II/e (economy).
Nios II/f
The Nios II/f core is designed for maximum performance at the expense of core size. Features of Nios II/f include:
Separate instruction and data caches (512 Bto 64 KB)
Optional JTAG debug module enhancements, including hardware breakpoints, data triggers, and real-time trace
Nios II/s
Nios II/s core is designed to maintain a balance between performance and cost. This core implementation is not longer supported for Altera Quartus II v.17 and newer. Features of Nios II/s include:
Optional JTAG debug module enhancements, including hardware breakpoints, data triggers, and real-time trace
Nios II/e
The Nios II/e core is designed for smallest possible logic utilization of FPGAs. This is especially efficient for low-cost Cyclone II FPGA applications. Features of Nios II/e include:
Error (169008): Can't turn on open-drain option for differential I/O pin HPS_DDR3_DQS_N[1] Error (169008): Can't turn on open-drain option for differential I/O pin HPS_DDR3_DQS_N[2] Error (169008): Can't turn on open-drain option for differential I/O pin HPS_DDR3_DQS_N[3] Error (169008): Can't turn on open-drain option for differential I/O pin HPS_DDR3_DQS_P[1] Error (169008): Can't turn on open-drain option for differential I/O pin HPS_DDR3_DQS_P[2] Error (169008): Can't turn on open-drain option for differential I/O pin HPS_DDR3_DQS_P[3] Info (11798): Fitter preparation operations ending: elapsed time is 00:00:00 Warning (169064): Following 85 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results Info (169065): Pin AUD_ADCLRCK has a permanently disabled output enable Info (169065): Pin AUD_BCLK has a permanently disabled output enable Info (169065): Pin AUD_DACLRCK has a permanently disabled output enable Info (169065): Pin DRAM_DQ[0] has a permanently disabled output enable Info (169065): Pin DRAM_DQ[1] has a permanently disabled output enable Info (169065): Pin DRAM_DQ[2] has a permanently disabled output enable Info (169065): Pin DRAM_DQ[3] has a permanently disabled output enable Info (169065): Pin DRAM_DQ[4] has a permanently disabled output enable Info (169065): Pin DRAM_DQ[5] has a permanently disabled output enable Info (169065): Pin DRAM_DQ[6] has a permanently disabled output enable Info (169065): Pin DRAM_DQ[7] has a permanently disabled output enable Info (169065): Pin DRAM_DQ[8] has a permanently disabled output enable Info (169065): Pin DRAM_DQ[9] has a permanently disabled output enable Info (169065): Pin DRAM_DQ[10] has a permanently disabled output enable Info (169065): Pin DRAM_DQ[11] has a permanently disabled output enable Info (169065): Pin DRAM_DQ[12] has a permanently disabled output enable Info (169065): Pin DRAM_DQ[13] has a permanently disabled output enable Info (169065): Pin DRAM_DQ[14] has a permanently disabled output enable Info (169065): Pin DRAM_DQ[15] has a permanently disabled output enable Info (169065): Pin FPGA_I2C_SDAT has a permanently disabled output enable Info (169065): Pin PS2_CLK has a permanently disabled output enable Info (169065): Pin PS2_CLK2 has a permanently disabled output enable Info (169065): Pin PS2_DAT has a permanently disabled output enable Info (169065): Pin PS2_DAT2 has a permanently disabled output enable Info (169065): Pin HPS_CONV_USB_N has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[8] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[9] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[10] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[11] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[12] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[13] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[14] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[15] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[16] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[17] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[18] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[19] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[20] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[21] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[22] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[23] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[24] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[25] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[26] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[27] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[28] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[29] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[30] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQ[31] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQS_N[1] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQS_N[2] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQS_N[3] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQS_P[1] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQS_P[2] has a permanently disabled output enable Info (169065): Pin HPS_DDR3_DQS_P[3] has a permanently disabled output enable Info (169065): Pin HPS_ENET_INT_N has a permanently disabled output enable Info (169065): Pin HPS_ENET_MDIO has a permanently disabled output enable Info (169065): Pin HPS_FLASH_DATA[0] has a permanently disabled output enable Info (169065): Pin HPS_FLASH_DATA[1] has a permanently disabled output enable Info (169065): Pin HPS_FLASH_DATA[2] has a permanently disabled output enable Info (169065): Pin HPS_FLASH_DATA[3] has a permanently disabled output enable Info (169065): Pin HPS_GPIO[0] has a permanently disabled output enable Info (169065): Pin HPS_GPIO[1] has a permanently disabled output enable Info (169065): Pin HPS_GSENSOR_INT has a permanently disabled output enable Info (169065): Pin HPS_I2C1_SCLK has a permanently disabled output enable Info (169065): Pin HPS_I2C1_SDAT has a permanently disabled output enable Info (169065): Pin HPS_I2C2_SCLK has a permanently disabled output enable Info (169065): Pin HPS_I2C2_SDAT has a permanently disabled output enable Info (169065): Pin HPS_I2C_CONTROL has a permanently disabled output enable Info (169065): Pin HPS_KEY has a permanently disabled output enable Info (169065): Pin HPS_LED has a permanently disabled output enable Info (169065): Pin HPS_SD_CMD has a permanently disabled output enable Info (169065): Pin HPS_SD_DATA[0] has a permanently disabled output enable Info (169065): Pin HPS_SD_DATA[1] has a permanently disabled output enable Info (169065): Pin HPS_SD_DATA[2] has a permanently disabled output enable Info (169065): Pin HPS_SD_DATA[3] has a permanently disabled output enable Info (169065): Pin HPS_SPIM_SS has a permanently disabled output enable Info (169065): Pin HPS_USB_DATA[0] has a permanently disabled output enable Info (169065): Pin HPS_USB_DATA[1] has a permanently disabled output enable Info (169065): Pin HPS_USB_DATA[2] has a permanently disabled output enable Info (169065): Pin HPS_USB_DATA[3] has a permanently disabled output enable Info (169065): Pin HPS_USB_DATA[4] has a permanently disabled output enable Info (169065): Pin HPS_USB_DATA[5] has a permanently disabled output enable Info (169065): Pin HPS_USB_DATA[6] has a permanently disabled output enable Info (169065): Pin HPS_USB_DATA[7] has a permanently disabled output enable Warning (169069): Following 216 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results Info (169070): Pin ADC_CONVST has GND driving its datain port Info (169070): Pin ADC_DIN has GND driving its datain port Info (169070): Pin ADC_SCLK has GND driving its datain port Info (169070): Pin AUD_DACDAT has GND driving its datain port Info (169070): Pin AUD_XCK has GND driving its datain port Info (169070): Pin DRAM_ADDR[0] has GND driving its datain port Info (169070): Pin DRAM_ADDR[1] has GND driving its datain port Info (169070): Pin DRAM_ADDR[2] has GND driving its datain port Info (169070): Pin DRAM_ADDR[3] has GND driving its datain port Info (169070): Pin DRAM_ADDR[4] has GND driving its datain port Info (169070): Pin DRAM_ADDR[5] has GND driving its datain port Info (169070): Pin DRAM_ADDR[6] has GND driving its datain port Info (169070): Pin DRAM_ADDR[7] has GND driving its datain port Info (169070): Pin DRAM_ADDR[8] has GND driving its datain port Info (169070): Pin DRAM_ADDR[9] has GND driving its datain port Info (169070): Pin DRAM_ADDR[10] has GND driving its datain port Info (169070): Pin DRAM_ADDR[11] has GND driving its datain port Info (169070): Pin DRAM_ADDR[12] has GND driving its datain port Info (169070): Pin DRAM_BA[0] has GND driving its datain port Info (169070): Pin DRAM_BA[1] has GND driving its datain port Info (169070): Pin DRAM_CAS_N has GND driving its datain port Info (169070): Pin DRAM_CKE has GND driving its datain port Info (169070): Pin DRAM_CLK has GND driving its datain port Info (169070): Pin DRAM_CS_N has GND driving its datain port Info (169070): Pin DRAM_LDQM has GND driving its datain port Info (169070): Pin DRAM_RAS_N has GND driving its datain port Info (169070): Pin DRAM_UDQM has GND driving its datain port Info (169070): Pin DRAM_WE_N has GND driving its datain port Info (169070): Pin FPGA_I2C_SCLK has GND driving its datain port Info (169070): Pin HEX0[0] has GND driving its datain port Info (169070): Pin HEX0[1] has GND driving its datain port Info (169070): Pin HEX0[2] has GND driving its datain port Info (169070): Pin HEX0[3] has GND driving its datain port Info (169070): Pin HEX0[4] has GND driving its datain port Info (169070): Pin HEX0[5] has GND driving its datain port Info (169070): Pin HEX0[6] has GND driving its datain port Info (169070): Pin HEX1[0] has GND driving its datain port Info (169070): Pin HEX1[1] has GND driving its datain port Info (169070): Pin HEX1[2] has GND driving its datain port Info (169070): Pin HEX1[3] has GND driving its datain port Info (169070): Pin HEX1[4] has GND driving its datain port Info (169070): Pin HEX1[5] has GND driving its datain port Info (169070): Pin HEX1[6] has GND driving its datain port Info (169070): Pin HEX2[0] has GND driving its datain port Info (169070): Pin HEX2[1] has GND driving its datain port Info (169070): Pin HEX2[2] has GND driving its datain port Info (169070): Pin HEX2[3] has GND driving its datain port Info (169070): Pin HEX2[4] has GND driving its datain port Info (169070): Pin HEX2[5] has GND driving its datain port Info (169070): Pin HEX2[6] has GND driving its datain port Info (169070): Pin HEX3[0] has GND driving its datain port Info (169070): Pin HEX3[1] has GND driving its datain port Info (169070): Pin HEX3[2] has GND driving its datain port Info (169070): Pin HEX3[3] has GND driving its datain port Info (169070): Pin HEX3[4] has GND driving its datain port Info (169070): Pin HEX3[5] has GND driving its datain port Info (169070): Pin HEX3[6] has GND driving its datain port Info (169070): Pin HEX4[0] has GND driving its datain port Info (169070): Pin HEX4[1] has GND driving its datain port Info (169070): Pin HEX4[2] has GND driving its datain port Info (169070): Pin HEX4[3] has GND driving its datain port Info (169070): Pin HEX4[4] has GND driving its datain port Info (169070): Pin HEX4[5] has GND driving its datain port Info (169070): Pin HEX4[6] has GND driving its datain port Info (169070): Pin HEX5[0] has GND driving its datain port Info (169070): Pin HEX5[1] has GND driving its datain port Info (169070): Pin HEX5[2] has GND driving its datain port Info (169070): Pin HEX5[3] has GND driving its datain port Info (169070): Pin HEX5[4] has GND driving its datain port Info (169070): Pin HEX5[5] has GND driving its datain port Info (169070): Pin HEX5[6] has GND driving its datain port Info (169070): Pin IRDA_TXD has GND driving its datain port Info (169070): Pin LEDR[0] has GND driving its datain port Info (169070): Pin LEDR[1] has GND driving its datain port Info (169070): Pin LEDR[2] has GND driving its datain port Info (169070): Pin LEDR[3] has GND driving its datain port Info (169070): Pin LEDR[4] has GND driving its datain port Info (169070): Pin LEDR[5] has GND driving its datain port Info (169070): Pin LEDR[6] has GND driving its datain port Info (169070): Pin LEDR[7] has GND driving its datain port Info (169070): Pin LEDR[8] has GND driving its datain port Info (169070): Pin LEDR[9] has GND driving its datain port Info (169070): Pin TD_RESET_N has GND driving its datain port Info (169070): Pin VGA_BLANK_N has GND driving its datain port Info (169070): Pin VGA_B[0] has GND driving its datain port Info (169070): Pin VGA_B[1] has GND driving its datain port Info (169070): Pin VGA_B[2] has GND driving its datain port Info (169070): Pin VGA_B[3] has GND driving its datain port Info (169070): Pin VGA_B[4] has GND driving its datain port Info (169070): Pin VGA_B[5] has GND driving its datain port Info (169070): Pin VGA_B[6] has GND driving its datain port Info (169070): Pin VGA_B[7] has GND driving its datain port Info (169070): Pin VGA_CLK has GND driving its datain port Info (169070): Pin VGA_G[0] has GND driving its datain port Info (169070): Pin VGA_G[1] has GND driving its datain port Info (169070): Pin VGA_G[2] has GND driving its datain port Info (169070): Pin VGA_G[3] has GND driving its datain port Info (169070): Pin VGA_G[4] has GND driving its datain port Info (169070): Pin VGA_G[5] has GND driving its datain port Info (169070): Pin VGA_G[6] has GND driving its datain port Info (169070): Pin VGA_G[7] has GND driving its datain port Info (169070): Pin VGA_HS has GND driving its datain port Info (169070): Pin VGA_R[0] has GND driving its datain port Info (169070): Pin VGA_R[1] has GND driving its datain port Info (169070): Pin VGA_R[2] has GND driving its datain port Info (169070): Pin VGA_R[3] has GND driving its datain port Info (169070): Pin VGA_R[4] has GND driving its datain port Info (169070): Pin VGA_R[5] has GND driving its datain port Info (169070): Pin VGA_R[6] has GND driving its datain port Info (169070): Pin VGA_R[7] has GND driving its datain port Info (169070): Pin VGA_SYNC_N has GND driving its datain port Info (169070): Pin VGA_VS has GND driving its datain port Info (169070): Pin HPS_DDR3_ADDR[13] has GND driving its datain port Info (169070): Pin HPS_DDR3_ADDR[14] has GND driving its datain port Info (169070): Pin HPS_DDR3_DM[1] has GND driving its datain port Info (169070): Pin HPS_DDR3_DM[2] has GND driving its datain port Info (169070): Pin HPS_DDR3_DM[3] has GND driving its datain port Info (169070): Pin HPS_ENET_GTX_CLK has GND driving its datain port Info (169070): Pin HPS_ENET_MDC has GND driving its datain port Info (169070): Pin HPS_ENET_TX_DATA[0] has GND driving its datain port Info (169070): Pin HPS_ENET_TX_DATA[1] has GND driving its datain port Info (169070): Pin HPS_ENET_TX_DATA[2] has GND driving its datain port Info (169070): Pin HPS_ENET_TX_DATA[3] has GND driving its datain port Info (169070): Pin HPS_ENET_TX_EN has GND driving its datain port Info (169070): Pin HPS_FLASH_DCLK has GND driving its datain port Info (169070): Pin HPS_FLASH_NCSO has GND driving its datain port Info (169070): Pin HPS_SD_CLK has GND driving its datain port Info (169070): Pin HPS_SPIM_CLK has GND driving its datain port Info (169070): Pin HPS_SPIM_MOSI has GND driving its datain port Info (169070): Pin HPS_UART_TX has GND driving its datain port Info (169070): Pin HPS_USB_STP has GND driving its datain port Info (169070): Pin AUD_ADCLRCK has VCC driving its datain port Info (169070): Pin AUD_BCLK has VCC driving its datain port Info (169070): Pin AUD_DACLRCK has VCC driving its datain port Info (169070): Pin DRAM_DQ[0] has VCC driving its datain port Info (169070): Pin DRAM_DQ[1] has VCC driving its datain port Info (169070): Pin DRAM_DQ[2] has VCC driving its datain port Info (169070): Pin DRAM_DQ[3] has VCC driving its datain port Info (169070): Pin DRAM_DQ[4] has VCC driving its datain port Info (169070): Pin DRAM_DQ[5] has VCC driving its datain port Info (169070): Pin DRAM_DQ[6] has VCC driving its datain port Info (169070): Pin DRAM_DQ[7] has VCC driving its datain port Info (169070): Pin DRAM_DQ[8] has VCC driving its datain port Info (169070): Pin DRAM_DQ[9] has VCC driving its datain port Info (169070): Pin DRAM_DQ[10] has VCC driving its datain port Info (169070): Pin DRAM_DQ[11] has VCC driving its datain port Info (169070): Pin DRAM_DQ[12] has VCC driving its datain port Info (169070): Pin DRAM_DQ[13] has VCC driving its datain port Info (169070): Pin DRAM_DQ[14] has VCC driving its datain port Info (169070): Pin DRAM_DQ[15] has VCC driving its datain port Info (169070): Pin FPGA_I2C_SDAT has VCC driving its datain port Info (169070): Pin PS2_CLK has VCC driving its datain port Info (169070): Pin PS2_CLK2 has VCC driving its datain port Info (169070): Pin PS2_DAT has VCC driving its datain port Info (169070): Pin PS2_DAT2 has VCC driving its datain port Info (169070): Pin HPS_CONV_USB_N has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[8] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[9] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[10] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[11] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[12] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[13] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[14] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[15] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[16] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[17] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[18] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[19] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[20] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[21] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[22] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[23] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[24] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[25] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[26] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[27] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[28] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[29] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[30] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQ[31] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQS_N[1] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQS_N[2] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQS_N[3] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQS_P[1] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQS_P[2] has VCC driving its datain port Info (169070): Pin HPS_DDR3_DQS_P[3] has VCC driving its datain port Info (169070): Pin HPS_ENET_INT_N has VCC driving its datain port Info (169070): Pin HPS_ENET_MDIO has VCC driving its datain port Info (169070): Pin HPS_FLASH_DATA[0] has VCC driving its datain port Info (169070): Pin HPS_FLASH_DATA[1] has VCC driving its datain port Info (169070): Pin HPS_FLASH_DATA[2] has VCC driving its datain port Info (169070): Pin HPS_FLASH_DATA[3] has VCC driving its datain port Info (169070): Pin HPS_GPIO[0] has VCC driving its datain port Info (169070): Pin HPS_GPIO[1] has VCC driving its datain port Info (169070): Pin HPS_GSENSOR_INT has VCC driving its datain port Info (169070): Pin HPS_I2C1_SCLK has VCC driving its datain port Info (169070): Pin HPS_I2C1_SDAT has VCC driving its datain port Info (169070): Pin HPS_I2C2_SCLK has VCC driving its datain port Info (169070): Pin HPS_I2C2_SDAT has VCC driving its datain port Info (169070): Pin HPS_I2C_CONTROL has VCC driving its datain port Info (169070): Pin HPS_KEY has VCC driving its datain port Info (169070): Pin HPS_LED has VCC driving its datain port Info (169070): Pin HPS_SD_CMD has VCC driving its datain port Info (169070): Pin HPS_SD_DATA[0] has VCC driving its datain port Info (169070): Pin HPS_SD_DATA[1] has VCC driving its datain port Info (169070): Pin HPS_SD_DATA[2] has VCC driving its datain port Info (169070): Pin HPS_SD_DATA[3] has VCC driving its datain port Info (169070): Pin HPS_SPIM_SS has VCC driving its datain port Info (169070): Pin HPS_USB_DATA[0] has VCC driving its datain port Info (169070): Pin HPS_USB_DATA[1] has VCC driving its datain port Info (169070): Pin HPS_USB_DATA[2] has VCC driving its datain port Info (169070): Pin HPS_USB_DATA[3] has VCC driving its datain port Info (169070): Pin HPS_USB_DATA[4] has VCC driving its datain port Info (169070): Pin HPS_USB_DATA[5] has VCC driving its datain port Info (169070): Pin HPS_USB_DATA[6] has VCC driving its datain port Info (169070): Pin HPS_USB_DATA[7] has VCC driving its datain port Info (169186): Following groups of pins have the same dynamic on-chip termination control Info (169185): Following pins have the same dynamic on-chip termination control: unnamed:u0|unnamed_hps_0:hps_0|unnamed_hps_0_hps_0:hps_0|unnamed_hps_0_hps_0_hps_io:hps_io|unnamed_hps_0_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|diff_dtc_bar Info (169066): Type bi-directional pin HPS_DDR3_DQS_N[0] uses the Differential 1.5-V SSTL Class I I/O standard Info (169185): Following pins have the same dynamic on-chip termination control: unnamed:u0|unnamed_hps_0:hps_0|unnamed_hps_0_hps_0:hps_0|unnamed_hps_0_hps_0_hps_io:hps_io|unnamed_hps_0_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin HPS_DDR3_DQ[0] uses the SSTL-15 Class I I/O standard Info (169185): Following pins have the same dynamic on-chip termination control: unnamed:u0|unnamed_hps_0:hps_0|unnamed_hps_0_hps_0:hps_0|unnamed_hps_0_hps_0_hps_io:hps_io|unnamed_hps_0_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin HPS_DDR3_DQ[1] uses the SSTL-15 Class I I/O standard Info (169185): Following pins have the same dynamic on-chip termination control: unnamed:u0|unnamed_hps_0:hps_0|unnamed_hps_0_hps_0:hps_0|unnamed_hps_0_hps_0_hps_io:hps_io|unnamed_hps_0_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin HPS_DDR3_DQ[2] uses the SSTL-15 Class I I/O standard Info (169185): Following pins have the same dynamic on-chip termination control: unnamed:u0|unnamed_hps_0:hps_0|unnamed_hps_0_hps_0:hps_0|unnamed_hps_0_hps_0_hps_io:hps_io|unnamed_hps_0_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin HPS_DDR3_DQ[3] uses the SSTL-15 Class I I/O standard Info (169185): Following pins have the same dynamic on-chip termination control: unnamed:u0|unnamed_hps_0:hps_0|unnamed_hps_0_hps_0:hps_0|unnamed_hps_0_hps_0_hps_io:hps_io|unnamed_hps_0_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin HPS_DDR3_DQ[4] uses the SSTL-15 Class I I/O standard Info (169185): Following pins have the same dynamic on-chip termination control: unnamed:u0|unnamed_hps_0:hps_0|unnamed_hps_0_hps_0:hps_0|unnamed_hps_0_hps_0_hps_io:hps_io|unnamed_hps_0_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin HPS_DDR3_DQ[5] uses the SSTL-15 Class I I/O standard Info (169185): Following pins have the same dynamic on-chip termination control: unnamed:u0|unnamed_hps_0:hps_0|unnamed_hps_0_hps_0:hps_0|unnamed_hps_0_hps_0_hps_io:hps_io|unnamed_hps_0_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin HPS_DDR3_DQ[6] uses the SSTL-15 Class I I/O standard Info (169185): Following pins have the same dynamic on-chip termination control: unnamed:u0|unnamed_hps_0:hps_0|unnamed_hps_0_hps_0:hps_0|unnamed_hps_0_hps_0_hps_io:hps_io|unnamed_hps_0_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin HPS_DDR3_DQ[7] uses the SSTL-15 Class I I/O standard Info (169185): Following pins have the same dynamic on-chip termination control: unnamed:u0|unnamed_hps_0:hps_0|unnamed_hps_0_hps_0:hps_0|unnamed_hps_0_hps_0_hps_io:hps_io|unnamed_hps_0_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|diff_dtc Info (169066): Type bi-directional pin HPS_DDR3_DQS_P[0] uses the Differential 1.5-V SSTL Class I I/O standard Error (11802): Can't fit design in device. Modify your design to reduce resources, or choose a larger device. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. Error: Quartus Prime Fitter was unsuccessful. 7 errors, 5 warnings Error: Peak virtual memory: 5113 megabytes Error: Processing ended: Sun Mar 22 17:55:31 2026 Error: Elapsed time: 00:00:06 Error: Total CPU time (on all processors): 00:00:05 Error (293001): Quartus Prime Full Compilation was unsuccessful. 9 errors, 341 warnings
quartus prime pro / standard 에서 지원한다고 하면 lite로는 쓸 수 없다는 말이네?
Intel® FPGA SDK for OpenCL • No additional licenses are required. • Supported with the Intel Quartus Prime Pro/Standard Edition Software. • The software installation file includes the Intel Quartus Prime Pro/Standard Edition Software and the OpenCL software.
Altera SDK for OpenCL Programming Guide에 의하면 13.0 그런데 이건 de1-soc용은 아닌듯.
■ Download and install the Quartus II software version 13.0. ■ Install your Stratix V FPGA board. You must download and install all necessary device support software. ■ Download the Altera SDK for OpenCL version 13.0. ■ Install the Altera SDK for OpenCL version 13.0. ■ Install the USB-Blaster and the PCI Express® (PCIe ®) drivers.
DE1-SoC openCL v05 문서를 terasic에서 받아서 보는데 18.1.0.625
음.. quartus prime standard edition with valid license.. 하... 1년 무상제공 이런것도 쿠폰이 없던데.. ㅠㅠ
Intel Quartus Prime Standard Edition 18.1.0.625 installed with valid license Intel FPGA SDK for OpenCL Prime Edition 18.1.0.625 installed without license Intel SoC EDS 18.1.0.625 installed
FPGA Starter Edition 자체는 무료지만, quartus prime standard는 유료..
quartus prime lite로 내려가야하나..?
그런데 21.1 부터는 modelsim 도 지원안한다고 하니 적당히(?) 더 구버전을 가야할 것 같기도 하다.
Questa*-인텔® FPGA Edition 빠른 시작: 인텔® Quartus® Prime Pro Edition페이지에서 라이선스를 얻는 방법에 대한 정보를 찾을 수 있습니다. *인텔® Quartus® Prime Pro Edition 21.3 이상 및 인텔® Quartus® Prime Standard/Lite Edition 21.1 이상부터 ModelSim*-인텔® FPGA Edition 및 ModelSim*-인텔® FPGA Starter Edition은 더 이상 지원되지 않습니다.
