| \CONFIGURATION OVERVIEW After power-on or reset, the AD4111 default configuration is as follows: • Channel configuration: Channel 0 is enabled, the VIN0 and VIN1 pair is selected as the input. Setup 0 is selected. • Setup configuration: the analog input buffers are disabled and the reference input buffers are also disabled. The REF± pins are selected as the reference source. Note that for this setup, the default channel does not operate correctly because the input buffers need to be enabled for a VIN input. • Filter configuration: the sinc5 + sinc1 filter is selected and the maximum output data rate of 31.25 kSPS is selected. • ADC mode: continuous conversion mode and the internal oscillator are enabled. The internal reference is disabled. • Interface mode: CRC and the data and status output are disabled. • GPIO configuration: open wire detection is disabled. Note that only a few of the register setting options are shown. This list is only an example. For full register information, see the Register Details section. Figure 35 shows an overview of the suggested flow for changing the ADC configuration, divided into the following three blocks: • Channel configuration (see Box A in Figure 35) • Setup configuration (see Box B in Figure 35) • ADC mode and interface mode configuration (see Box C in Figure 35)  SPI의 MISO핀이 RDY라서 어떻게 읽나 했는데 상태 레지스터에서 RDY를 보면 된다.  CONTINUOUS CONVERSION MODE Continuous conversion mode is the default power-up mode. The AD4111 converts continuously, and the RDY bit in the status register goes low each time a conversion is complete. If CS is low, the RDY output also goes low when a conversion is complete SINGLE CONVERSION MODE In single conversion mode, the AD4111 performs a single conversion and is placed in standby mode after the conversion is complete. The RDY output goes low to indicate the completion of a conversion. When the data-word has been read from the data register, the RDY output goes high. The data register can be read several times, if required, even when the RDY output goes high. If several channels are enabled, the ADC automatically sequences through the enabled channels and performs a conversion on each channel. When the first conversion is started, the RDY output goes high and remains high until a valid conversion is available and CS is low. When the conversion is available, the RDY output goes low. The ADC then selects the next channel and begins a conversion. The user can read the present conversion while the next conversion is being performed. When the next conversion is complete, the data register is updated; therefore, the user has a limited period in which to read the conversion. When the ADC has performed a single conversion on each of the selected channels, it returns to standby mode. If the DATA_STAT bit in the interface mode register is set to 1, the contents of the status register, along with the conversion, are output each time the data register is read. The four LSBs of the status register indicate the channel to which the conversion corresponds.   |
[링크 : https://www.analog.com/media/en/technical-documentation/data-sheets/ad4111.pdf]
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