구차니의 잡동사니 모음

"VGA industry standard" 640x480 pixel mode

Clock frequency 25.175 MHz

Line  frequency 31469 Hz

Field frequency 59.94 Hz

One line

  8 pixels front porch

96 pixels horizontal sync

 40 pixels back porch

  8 pixels left border

640 pixels video

  8 pixels right border

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800 pixels total per line

One field

  2 lines front porch

  2 lines vertical sync

 25 lines back porch

  8 lines top border

480 lines video

  8 lines bottom border

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525 lines total per field               

Pins 1 through 9 carry the three TMDS data channels (Transition Minimized Differential Signaling – the technology that allows DVI and HDMI to send high-speed digital data), three pins per channel. TMDS data includes both video and audio information, and each channel has three separate lines for + values, - values, and a ground or data shield.

Pins 10 through 12 carry data for the TMDS clock channel, which helps keep the signals in synchronization. As with the TMDS data channels, there are separate lines for + values, - values, and a data shield.

Pin 13 is carries the CEC (Consumer Electronics Control) channel, used for sending command and control data between connected devices.

Pin 14 is reserved for future use.

Pins 15 and 16 are dedicated to the DDC (Display Data Channel), used for communicating EDID (Extended Display Identification Channel) information between devices.

Pin 17 is a data shield for the CEC and DDC channels.

Pin 18 carries a low-voltage (+5V) power supply.

Pin 19 is the Hot Plug Detect, dedicated to monitoring power up/down and plug/unplug events. 

Basics

 HDMI leverages on the successful transition minimized differential signaling (TMDS) technology. The differential signals are +3.3 Volts, terminated in 50 Ω with nominal amplitude transitions of 500 mV (+2.8 V to +3.3 V). The voltage swing can vary from 150 mV to 800 mV. The signals have rise times of the order of 100 ps 

6.2.2 Video Control Signals : HSYNC, VSYNC

During the Data Island period, HDMI carries HSYNC and VSYNC signals using encoded bits on Channel 0. During Video Data periods, HDMI does not carry HSYNC and VSYNC and the Sink should assume that these signals remain constant. During Control periods, HDMI carries HSYNC and VSYNC signals through the use of four different control characters on TMDS Channel 0. 

A VGA video signal contains 5 active signals:

• horizontal sync: digital signal, used for synchronisation of the video

• vertical sync: digital signal, used for synchronisation of the video

• red (R): analog signal (0-0.7 v), used to control the color

• green (G): analog signal (0-0.7 v), used to control the color

• blue (B): analog signal (0-0.7 v), used to control the color 

Three update protocols are utilized. On UART, SSI, I2C, and CAN, a custom protocol is used to communicate with the download utility to transfer the firmware image and program it into flash. When using Ethernet or USB DFU, however, different protocols are employed. On Ethernet the standard bootstrap protocol (BOOTP) is used and for USB DFU, updates are performed via the standard Device Firmware Upgrade (DFU) class. 

USB Device Firmware Upgrade (DFU) is an official USB device class specification of the USB Implementers Forum.

It specifies a vendor and device independent way of updating the firmware of a USB device. The idea is to have only one vendor-independent firmware update tool as part of the operating system, which can then (given a particular firmware image) be downloaded into the device. 

A+B=R (OR)

 AxB=R (AND)

F+F=F

T+F=T

F+T=T

T+T=T

FxF=F

TxF=F

FxT=F

TxT=T

A+B=R (OR)

 AxB=R (AND)

F+F=F

1+F=T

F+1=T

T+T=T

FxF=F

1xF=F 는 곧 1xA=A

Fx1=F 는 곧 Ax1=A

TxT=T

(X+Y)'=R 

F+F=F가 F' = T

T+F=T가 T' = F

F+T=T가 T' = F

T+T=T가 T' = F

AxB=R

FxF=F

TxF=F

FxT=F

TxT=T

A'xB'=R

F'xF'=TxT=T

T'xF'=FxT=F

F'xT'=TxF=F

T'xT'=FxF=F