구차니의 잡동사니 모음

• UltraScale+ GTR (6.0 Gb/s): Easiest integration of common protocols to the Zynq Processor Subsystem
• UltraScale+ GTH (16.3 Gb/s): Low power & high performance for the toughest backplanes
• UltraScale+ GTY (32.75 Gb/s): Maximum NRZ performance for the fastest optical and backplane applications; 33G transceivers for chip-to-chip, chip-to-optics, and 28G backplanes
• UltraScale GTH (16.3 Gb/s): Low power & high performance for the toughest backplanes
• UltraScale GTY (30.5 Gb/s): High performance for optical and backplane applications; 30G transceivers for chip-to-chip, chip-to-optics, and 28G backplanes
• UltraScale+ GTM (58 Gb/s): Maximum performance using PAM4 for 58G chip-to-chip, chip-to-optics, and backplane applications
• 7 Series GTP (6.6 Gb/s): Power optimized transceiver for consumer and legacy serial standards
• 7 Series GTX (12.5 Gb/s): Lowest jitter and strongest equalization in a mid-range transceiver
• 7 Series GTH (13.1 Gb/s): Backplane and optical performance through world class jitter and equalization
• 7 Series GTZ (28.05 Gb/s): Highest rate, lowest jitter 28G transceiver in a 28nm FPGA
• Spartan-6 GTP (3.2 Gb/s): Power and cost optimized transceiver for cost-sensitive applications

The original plan was the smaller Artix would not have the AES/HMAC and XADC blocks.

This was changed pretty recently - now all 7 series devices will be uniform in the support of these features. 

Encryption, Readback, and Partial Reconfiguration

In all 7 series FPGAs (except XC7S6 and XC7S15), the FPGA bitstream, which contains sensitive customer IP, can be protected with 256-bit AES encryption and HMAC/SHA-256 authentication to prevent unauthorized copying of the design. The FPGA performs decryption on the fly during configuration using an internally stored 256-bit key. This key can reside in battery-backed RAM or in nonvolatile eFUSE bits. Most configuration data can be read back without affecting the system's operation. Typically, configuration is an all-or-nothing operation, but Xilinx 7 series FPGAs support partial reconfiguration. This is an extremely powerful and flexible feature that allows the user to change portions of the FPGA while other portions remain static. Users can time-slice these portions to fit more IP into smaller devices, saving cost and power. Where applicable in certain designs, partial reconfiguration can greatly improve the versatility of the FPGA.