'embeded/Cortex-M7 STM' 카테고리의 글 목록

'embeded/Cortex-M7 STM'에 해당되는 글 36건

2026.03.13 stm32h757 링커 스크립트
2026.03.13 stm32h757 메모리(SRAM) 구조
2026.02.03 stm32f7 dual bank flash
2026.02.03 stm32f746g-disco with semtech sx1276 and lvgl
2024.10.10 modbus rtu coil read
2024.10.08 stm32 __weak
2024.09.26 stm32 modbus
2024.09.11 SPI NSS, NSSP mode
2024.09.06 FDE CIE
2024.09.06 code alignement factor?

stm32h757 링커 스크립트

cubeide로 생성해서 일단 비교

CM7 ld

/*
******************************************************************************
**
**  File        : LinkerScript.ld
**
**  Author      : STM32CubeIDE
**
**  Abstract    : Linker script for STM32H7 series
**                      1024Kbytes FLASH
**                      800Kbytes RAM
**
**                Set heap size, stack size and stack location according
**                to application requirements.
**
**                Set memory bank area and size if external memory is used.
**
**  Target      : STMicroelectronics STM32
**
**  Distribution: The file is distributed as is without any warranty
**                of any kind.
**
*****************************************************************************
** @attention
**
** Copyright (c) 2024 STMicroelectronics.
** All rights reserved.
**
** This software is licensed under terms that can be found in the LICENSE file
** in the root directory of this software component.
** If no LICENSE file comes with this software, it is provided AS-IS.
**
*****************************************************************************
*/

/* Entry Point */
ENTRY(Reset_Handler)

/* Highest address of the user mode stack */
_estack = ORIGIN(RAM_D1) + LENGTH(RAM_D1); /* end of "RAM_D1" Ram type memory */

_Min_Heap_Size = 0x200; /* required amount of heap  */
_Min_Stack_Size = 0x400; /* required amount of stack */

/* Memories definition */
MEMORY
{
  RAM_D1 (xrw)   : ORIGIN = 0x24000000, LENGTH =  512K
  FLASH   (rx)   : ORIGIN = 0x08000000, LENGTH = 1024K    /* Memory is divided. Actual start is 0x08000000 and actual length is 2048K */
  DTCMRAM (xrw)  : ORIGIN = 0x20000000, LENGTH = 128K
  RAM_D2 (xrw)   : ORIGIN = 0x30000000, LENGTH = 288K
  RAM_D3 (xrw)   : ORIGIN = 0x38000000, LENGTH = 64K
  ITCMRAM (xrw)  : ORIGIN = 0x00000000, LENGTH = 64K
}

/* Sections */
SECTIONS
{
  /* The startup code into "FLASH" Rom type memory */
  .isr_vector :
  {
    . = ALIGN(4);
    KEEP(*(.isr_vector)) /* Startup code */
    . = ALIGN(4);
  } >FLASH

  /* The program code and other data into "FLASH" Rom type memory */
  .text :
  {
    . = ALIGN(4);
    *(.text)           /* .text sections (code) */
    *(.text*)          /* .text* sections (code) */
    *(.glue_7)         /* glue arm to thumb code */
    *(.glue_7t)        /* glue thumb to arm code */
    *(.eh_frame)

    KEEP (*(.init))
    KEEP (*(.fini))

    . = ALIGN(4);
    _etext = .;        /* define a global symbols at end of code */
  } >FLASH

  /* Constant data into "FLASH" Rom type memory */
  .rodata :
  {
    . = ALIGN(4);
    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
    . = ALIGN(4);
  } >FLASH

  .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
  {
    . = ALIGN(4);
    *(.ARM.extab* .gnu.linkonce.armextab.*)
    . = ALIGN(4);
  } >FLASH
  .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
  {
    . = ALIGN(4);
    __exidx_start = .;
    *(.ARM.exidx*)
    __exidx_end = .;
    . = ALIGN(4);
  } >FLASH

  .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
  {
    . = ALIGN(4);
    PROVIDE_HIDDEN (__preinit_array_start = .);
    KEEP (*(.preinit_array*))
    PROVIDE_HIDDEN (__preinit_array_end = .);
    . = ALIGN(4);
  } >FLASH

  .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
  {
    . = ALIGN(4);
    PROVIDE_HIDDEN (__init_array_start = .);
    KEEP (*(SORT(.init_array.*)))
    KEEP (*(.init_array*))
    PROVIDE_HIDDEN (__init_array_end = .);
    . = ALIGN(4);
  } >FLASH

  .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
  {
    . = ALIGN(4);
    PROVIDE_HIDDEN (__fini_array_start = .);
    KEEP (*(SORT(.fini_array.*)))
    KEEP (*(.fini_array*))
    PROVIDE_HIDDEN (__fini_array_end = .);
    . = ALIGN(4);
  } >FLASH

  /* Used by the startup to initialize data */
  _sidata = LOADADDR(.data);

  /* Initialized data sections into "RAM" Ram type memory */
  .data :
  {
    . = ALIGN(4);
    _sdata = .;        /* create a global symbol at data start */
    *(.data)           /* .data sections */
    *(.data*)          /* .data* sections */
    *(.RamFunc)        /* .RamFunc sections */
    *(.RamFunc*)       /* .RamFunc* sections */

    . = ALIGN(4);
    _edata = .;        /* define a global symbol at data end */
  } >RAM_D1 AT> FLASH

  /* Uninitialized data section into "RAM" Ram type memory */
  . = ALIGN(4);
  .bss :
  {
    /* This is used by the startup in order to initialize the .bss section */
    _sbss = .;         /* define a global symbol at bss start */
    __bss_start__ = _sbss;
    *(.bss)
    *(.bss*)
    *(COMMON)

    . = ALIGN(4);
    _ebss = .;         /* define a global symbol at bss end */
    __bss_end__ = _ebss;
  } >RAM_D1

  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
  ._user_heap_stack :
  {
    . = ALIGN(8);
    PROVIDE ( end = . );
    PROVIDE ( _end = . );
    . = . + _Min_Heap_Size;
    . = . + _Min_Stack_Size;
    . = ALIGN(8);
  } >RAM_D1

  /* Remove information from the compiler libraries */
  /DISCARD/ :
  {
    libc.a ( * )
    libm.a ( * )
    libgcc.a ( * )
  }

  .ARM.attributes 0 : { *(.ARM.attributes) }
}

CM4 ld

/*
******************************************************************************
**
**  File        : LinkerScript.ld
**
**  Author      : STM32CubeIDE
**
**  Abstract    : Linker script for STM32H7 series
**                1024Kbytes FLASH and 288Kbytes RAM
**
**                Set heap size, stack size and stack location according
**                to application requirements.
**
**                Set memory bank area and size if external memory is used.
**
**  Target      : STMicroelectronics STM32
**
**  Distribution: The file is distributed as is, without any warranty
**                of any kind.
**
*****************************************************************************
** @attention
**
** Copyright (c) 2024 STMicroelectronics.
** All rights reserved.
**
** This software is licensed under terms that can be found in the LICENSE file
** in the root directory of this software component.
** If no LICENSE file comes with this software, it is provided AS-IS.
**
****************************************************************************
*/

/* Entry Point */
ENTRY(Reset_Handler)

/* Highest address of the user mode stack */
_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of RAM */
/* Generate a link error if heap and stack don't fit into RAM */
_Min_Heap_Size = 0x200;      /* required amount of heap  */
_Min_Stack_Size = 0x400; /* required amount of stack */

/* Specify the memory areas */
MEMORY
{
FLASH (rx)     : ORIGIN = 0x08100000, LENGTH = 1024K
RAM (xrw)      : ORIGIN = 0x10000000, LENGTH = 288K
}

/* Define output sections */
SECTIONS
{
  /* The startup code goes first into FLASH */
  .isr_vector :
  {
    . = ALIGN(4);
    KEEP(*(.isr_vector)) /* Startup code */
    . = ALIGN(4);
  } >FLASH

  /* The program code and other data goes into FLASH */
  .text :
  {
    . = ALIGN(4);
    *(.text)           /* .text sections (code) */
    *(.text*)          /* .text* sections (code) */
    *(.glue_7)         /* glue arm to thumb code */
    *(.glue_7t)        /* glue thumb to arm code */
    *(.eh_frame)

    KEEP (*(.init))
    KEEP (*(.fini))

    . = ALIGN(4);
    _etext = .;        /* define a global symbols at end of code */
  } >FLASH

  /* Constant data goes into FLASH */
  .rodata :
  {
    . = ALIGN(4);
    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
    . = ALIGN(4);
  } >FLASH

  .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
  {
    *(.ARM.extab* .gnu.linkonce.armextab.*)
  } >FLASH
  .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
  {
    __exidx_start = .;
    *(.ARM.exidx*)
    __exidx_end = .;
  } >FLASH

  .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
  {
    PROVIDE_HIDDEN (__preinit_array_start = .);
    KEEP (*(.preinit_array*))
    PROVIDE_HIDDEN (__preinit_array_end = .);
  } >FLASH
  .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
  {
    PROVIDE_HIDDEN (__init_array_start = .);
    KEEP (*(SORT(.init_array.*)))
    KEEP (*(.init_array*))
    PROVIDE_HIDDEN (__init_array_end = .);
  } >FLASH
  .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
  {
    PROVIDE_HIDDEN (__fini_array_start = .);
    KEEP (*(SORT(.fini_array.*)))
    KEEP (*(.fini_array*))
    PROVIDE_HIDDEN (__fini_array_end = .);
  } >FLASH

  /* used by the startup to initialize data */
  _sidata = LOADADDR(.data);

  /* Initialized data sections goes into RAM, load LMA copy after code */
  .data :
  {
    . = ALIGN(4);
    _sdata = .;        /* create a global symbol at data start */
    *(.data)           /* .data sections */
    *(.data*)          /* .data* sections */
    *(.RamFunc)        /* .RamFunc sections */
    *(.RamFunc*)       /* .RamFunc* sections */

    . = ALIGN(4);
    _edata = .;        /* define a global symbol at data end */
  } >RAM AT> FLASH

  /* Uninitialized data section */
  . = ALIGN(4);
  .bss :
  {
    /* This is used by the startup in order to initialize the .bss section */
    _sbss = .;         /* define a global symbol at bss start */
    __bss_start__ = _sbss;
    *(.bss)
    *(.bss*)
    *(COMMON)

    . = ALIGN(4);
    _ebss = .;         /* define a global symbol at bss end */
    __bss_end__ = _ebss;
  } >RAM

  /* User_heap_stack section, used to check that there is enough RAM left */
  ._user_heap_stack :
  {
    . = ALIGN(8);
    PROVIDE ( end = . );
    PROVIDE ( _end = . );
    . = . + _Min_Heap_Size;
    . = . + _Min_Stack_Size;
    . = ALIGN(8);
  } >RAM

  /* Remove information from the standard libraries */
  /DISCARD/ :
  {
    libc.a ( * )
    libm.a ( * )
    libgcc.a ( * )
  }

  .ARM.attributes 0 : { *(.ARM.attributes) }
}

저작자표시 (새창열림)

'embeded > Cortex-M7 STM' 카테고리의 다른 글

stm32h757 메모리(SRAM) 구조 (0)	2026.03.13
stm32f7 dual bank flash (0)	2026.02.03
stm32f746g-disco with semtech sx1276 and lvgl (0)	2026.02.03
modbus rtu coil read (0)	2024.10.10
stm32 __weak (0)	2024.10.08

Posted by 구차니

stm32h757 메모리(SRAM) 구조

링커 스크립트를 보면 아래와 같이 메모리가 희한하게 많다.

/* Memories definition */
MEMORY
{
  RAM_D1 (xrw)   : ORIGIN = 0x24000000, LENGTH =  512K
  BOOT   (rx)   : ORIGIN = 0x08000000, LENGTH = 128K
  DTCMRAM (xrw)  : ORIGIN = 0x20000000, LENGTH = 128K
  RAM_D2 (xrw)   : ORIGIN = 0x30000000, LENGTH = 288K
  RAM_D3 (xrw)   : ORIGIN = 0x38000000, LENGTH = 64K
  ITCMRAM (xrw)  : ORIGIN = 0x00000000, LENGTH = 64K
}

아무래도 M7 에는 TCM 으로 바로 붙어 있어서 가장 빠르게 접근이 될 거고

M4의 경우 AHB 를 거쳐야 해서 M7의 TCM 보다는 접근 속도가 느릴듯 하다.

D1 domain 에는 Cortex-M7에 붙어있는 ITCM 64K / DTCM 128K(TCM - Tightly Coupled Memory)

D2 domain 에는 Cortex-M4에 가까운 SRAM1 128K(I-bus) / SRAM2 128K(D-bus) / SRAM3 32K(S-bus)가 존재한다.

D3 domain 에는 SRAM4 64K / Backup SRAM 4K 가 존재한다.(얘네는 링커에 없다)

3.3.3 Embedded SRAM
All devices feature around 1 Mbyte of RAM with hardware ECC. The RAM is divided as
follows:
• 512 Kbytes of AXI-SRAM mapped onto AXI bus on D1 domain.
• SRAM1 mapped on D2 domain: 128 Kbytes
• SRAM2 mapped on D2 domain: 128 Kbytes
• SRAM3 mapped on D2 domain: 32 Kbytes
• SRAM4 mapped on D3 domain: 64 Kbytes
• 4 Kbytes of backup SRAM
The content of this area is protected against possible unwanted write accesses,
and is retained in Standby or VBAT mode.
• RAM mapped to TCM interface (ITCM and DTCM):
Both ITCM and DTCM RAMs are 0 wait state memories. They can be accessed either
from the Arm® Cortex®-M7 CPU or the MDMA (even in Sleep mode) through a specific
AHB slave of the Cortex®-M7(AHBS):
– 64 Kbytes of ITCM-RAM (instruction RAM)
This RAM is connected to ITCM 64-bit interface designed for execution of critical
real-times routines by the Cortex®-M7.
– 128 Kbytes of DTCM-RAM (2x 64-Kbyte DTCM-RAMs on 2x32-bit DTCM ports)
The DTCM-RAM could be used for critical real-time data, such as interrupt service
routines or stack/heap memory. Both DTCM-RAMs can be used in parallel (for
load/store operations) thanks to the Cortex®-M7 dual issue capability.
The MDMA can be used to load code or data in ITCM or DTCM RAMs.

[링크 : https://www.st.com/resource/en/datasheet/stm32h757ai.pdf]

M4가 M7 보다 메모리 어드레스 비트가 낮은가? 아무튼 아래와 같이 연결이 된다고 한다.

	cortex-M7	cortex-M4
AXI SRAM	0x2400 0000	?
SRAM1	0x3000 0000	0x1000 0000
SRAM2	0x3002 0000	0x1002 0000
SRAM3	0x3004 0000	0x1004 0000
SRAM4	0x3800 0000	?

2.2.1 Embedded SRAM
The STM32H7 dual‑core devices feature:
• Up to 864 Kbytes of System SRAM
• 128 Kbytes of data TCM RAM, DTCM RAM
• 64 Kbytes of instruction TCM RAM, ITCM RAM
• 4 Kbytes of backup SRAM
The embedded system SRAM is split into five blocks over the three power domains: AXI SRAM, AHB SRAM1,
AHB SRAM2, AHB SRAM3 and AHB SRAM4.
• D1 domain, AXI SRAM:
– AXI SRAM is accessible through D1 domain AXI bus matrix. It is mapped at address 0x2400 0000 and
accessible by all system masters except BDMA. AXI SRAM can be used for application data which are
not allocated in DTCM RAM or reserved for graphic objects (such as frame buffers)
• D2 domain, AHB SRAM:
– AHB SRAM1 is accessible through D2 domain AHB matrix. It is mapped at address 0x3000 0000 and
accessible by all system masters except BDMA. The AHB SRAMs of the D2 domain are also aliased
to an address range below 0x2000 0000 to maintain the Cortex®‑M4 Harvard architecture. The AHB
SRAM1 also mapped at address 0x1000 0000. The AHB SRAM2 also mapped at address 0x1002
0000. The AHB SRAM3 also mapped at address 0x1004 0000. All those AHB SRAMs are accessible
by all system masters through D2 domain AHB matrix. All those AHB SRAMs are accessible by all
system masters through D2 domain AHB matrix.
AHB SRAM1 can be used as DMA buffers to store peripheral input/output data in D2 domain, or as
code location for Cortex®‑M4 CPU (application code available when D1 is powered off). AHB SRAM1
can be used as DMA buffers to store peripheral input/output data in D2 domain, or as code location for
Cortex®‑M4 CPU (application code available when D1 is powered off).
– AHB SRAM2 is accessible through D2 domain AHB matrix. It is mapped at address 0x3002 0000
and accessible by all system masters except BDMA. AHB SRAM2 can be used as DMA buffers to
store peripheral input/output data in D2 domain, or as readwrite segment for application running on
Cortex®‑M4 CPU.
– AHB SRAM3 is accessible through D2 domain AHB matrix is mapped at address 0x3004 0000
and accessible by all system masters except BDMA. AHB SRAM3 can be used as buffers to store
peripheral input/output data for Ethernet and USB, or as shared memory between the two cores.
• D3 domain, AHB SRAM:
– AHB SRAM4 is mapped at address 0x3800 0000 and accessible by most of system masters through
D3 domain AHB matrix. AHB SRAM4 can be used as BDMA buffers to store peripheral input/output
data in D3 domain. It can also be used to retain some application code/data when D1 and D2 domain
in DStandby mode, or as shared memory between the two cores.
The system AHB SRAM can be accessed as bytes, half‑words (16‑bit units) or words (32‑bit units), while the
system AXI SRAM can be accessed as bytes, half‑words, words or doublewords (64‑bit units). These memories
can be addressed at maximum system clock frequency without wait state.

[링크 : https://www.st.com/resource/en/application_note/an5557-stm32h745755-and-stm32h747757-lines-dualcore-architecture-stmicroelectronics.pdf]

저작자표시 (새창열림)

'embeded > Cortex-M7 STM' 카테고리의 다른 글

stm32h757 링커 스크립트 (0)	2026.03.13
stm32f7 dual bank flash (0)	2026.02.03
stm32f746g-disco with semtech sx1276 and lvgl (0)	2026.02.03
modbus rtu coil read (0)	2024.10.10
stm32 __weak (0)	2024.10.08

Posted by 구차니

stm32f7 dual bank flash

페이지라고 해야하나.. 아무튼 섹터별로 용량이 균등하지 않은 녀석도 있다.

그리고 듀얼 뱅크와 싱글 뱅크의 경우 일종의 raid 0 처럼 분할해서 striping 되어 저장된다.

[링크 : https://www.st.com/resource/en/application_note/an4826-stm32f7-series-flash-memory-dual-bank-mode-stmicroelectronics.pdf]

저작자표시 (새창열림)

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stm32h757 링커 스크립트 (0)	2026.03.13
stm32h757 메모리(SRAM) 구조 (0)	2026.03.13
stm32f746g-disco with semtech sx1276 and lvgl (0)	2026.02.03
modbus rtu coil read (0)	2024.10.10
stm32 __weak (0)	2024.10.08

Posted by 구차니

stm32f746g-disco with semtech sx1276 and lvgl

액정은 큰 거 치고는 해상도가 낮다.

그래도 PSP 해상도라고(!) 130,560 pixel 이고 320x240의 76,800 pixel 에 비하면 거의 2배에 가까운 나름(!) 고해상도다.

STM32F746NGH6 Arm® Cortex® core-based microcontroller with 1 Mbyte of Flash memory and 340 Kbytes of RAM, in BGA216 package
4.3” RGB 480×272 color LCD-TFT with capacitive touch screen
Ethernet compliant with IEEE-802.3-2002
USB OTG HS
USB OTG FS
SAI audio codec
Two ST-MEMS digital microphones
128-Mbit Quad-SPI Flash memory

128-Mbit SDRAM (64 Mbits accessible)

[링크 : https://www.st.com/en/evaluation-tools/32f746gdiscovery.html]

이건 또 어떻게 살리냐..

[링크 : https://www.semtech.com/products/wireless-rf/lora-connect/sx1276mb1las]

일단 이거부터 빌드해서 넣어보자!

[링크 : https://github.com/lvgl/lv_port_stm32f746_disco]

응~ 에러

라는데 웃긴건 elf 파일이 생성되어 있다.

arm-none-eabi-gcc -o "lv_port_stm32f746_disco.elf" @"objects.list"   -mcpu=cortex-m7 -T"/home/falinux/work/src/lv_port_stm32f746_disco/LinkerScript.ld" --specs=nosys.specs -Wl,-Map="lv_port_stm32f746_disco.map" -Wl,--gc-sections -static --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -Wl,--start-group -lc -lm -Wl,--end-group
/opt/st/stm32cubeide_1.16.0/plugins/cohttp://m.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.linux64_1.0.200.202406132123/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/bin/ld: warning: /opt/st/stm32cubeide_1.16.0/plugins/cohttp://m.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.linux64_1.0.200.202406132123/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+fp/hard/crtn.o: missing .note.GNU-stack section implies executable stack
/opt/st/stm32cubeide_1.16.0/plugins/cohttp://m.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.linux64_1.0.200.202406132123/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/bin/ld: NOTE: This behaviour is deprecated and will be removed in a future version of the linker
/opt/st/stm32cubeide_1.16.0/plugins/cohttp://m.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.linux64_1.0.200.202406132123/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/bin/ld: warning: lv_port_stm32f746_disco.elf has a LOAD segment with RWX permissions
Finished building target: lv_port_stm32f746_disco.elf

arm-none-eabi-size  lv_port_stm32f746_disco.elf
   text    data     bss     dec     hex filename
617604    1064 204368 823036   c8efc lv_port_stm32f746_disco.elf
Finished building: default.size.stdout
arm-none-eabi-objdump -h -S lv_port_stm32f746_disco.elf  > "lv_port_stm32f746_disco.list"

arm-none-eabi-objcopy  -O binary lv_port_stm32f746_disco.elf  "lv_port_stm32f746_disco.bin"
Finished building: lv_port_stm32f746_disco.bin

Finished building: lv_port_stm32f746_disco.list

12:38:35 Build Failed. 1 errors, 2 warnings. (took 53s.960ms)

cortex-m7 이라 기대했는데 해상도 때문인가 느리다?!

저작자표시 (새창열림)

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modbus rtu coil read

modbus poll 에서 뜬금없이 crc error로 띄워서 헤맸는데

03이나 04 명령어 처럼 multiple byte의 경우에는 아래의 형태로 구성되는데

station_id / cmd / length / data(word) / crc

01의 경우는 아래의 형태로 고정된다.

station_id / cmd / length / data(byte) / crc

그러다 보니 modbud poll 에서도 고정된 length에서 하드코딩될수 밖에 없고

0x01 0x01 0x02 0x00 0x00 L_CRC M_CRC 로 응답하면

CRC 부분을 보고 읽는게 아니라

0x00 L_CRC 두개를 CRC로 해석하니 mismatch로 잘못 에러를 출력한다.

어우.. 별거 아닌데 하루를 날리게 하다니..

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stm32 __weak

인터럽트 핸들러의 경우 __WEAK가 앞에 붙어있는데

c 언어라면 동일한 함수명은 사용이 불가능한게 상식인데

새로 정의하면 새로 정의된 함수가 사용되고 기존에 정의된 함수는 사용되지 않는 신기한 녀석이다

그래서 이 기회에서 찾아보는 중

cmsis_armcc.h 에서 아래와 같이 정의되어 있다.

#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif

링크 시간에 strong symbol은 weak symbol을 override 한다. 라고 되어있는데

컴파일러가 아니라 링커가 연결해주는거라니 신기하다.

__attribute__((weak)) variable attribute
Generates a weak symbol for a variable, rather than the default symbol.

Syntax

__attribute__((weak)) <type> <variable>;
Parameters
None.

Operation
At link time, strong symbols override weak symbols. This attribute replaces a weak symbol with a strong symbol, by choosing a particular combination of object files to link.

Example

__attribute__((weak)) int foo;

[링크 : https://developer.arm.com/documentation/101754/0622/armclang-Reference/Compiler-specific-Function--Variable--and-Type-Attributes/--attribute----weak---variable-attribute]

[링크 : https://blog.naver.com/22wowow22/220825653093]

[링크 : https://gangsanilee.tistory.com/2874]

[링크 : https://tigershin-shinhyeonkyu.tistory.com/8]

[링크 : https://engineering-agit.tistory.com/25]

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stm32 modbus

은근 없네 -_-

FreeRTOS + STM32 HAL
[링크 : https://github.com/alejoseb/Modbus-STM32-HAL-FreeRTOS]

FreeRTOS + STM32 HAL
[링크 : https://github.com/eziya/STM32_HAL_FREEMODBUS_RTU]
[링크 : https://blog.naver.com/eziya76/220970378890]

stm32f[134] - MIT
[링크 : https://github.com/urands/stModbus]

gplv3 / misra check
[링크 : https://github.com/feaser/microtbx-modbus]
[링크 : https://www.feaser.com/en/blog/2023/04/stm32-modbus-rtu-server-tutorial/]

license 정보 미확인
[링크 : http://comfilewiki.co.kr/en/doku.php?id=comfilehmi:simplemodbus:simplemodbus_source:index]
[링크 : https://m.blog.naver.com/comfae/221664790332

simplemodbus(?)
[링크 : https://github.com/charlesbaynham/simple-modbus]

[링크 : https://community.st.com/t5/stm32-mcus-products/modbus-rtu-on-stm32l031g4/td-p/198871]

[링크 : https://github.com/debevv/nanoMODBUS] MIT

[링크 : https://github.com/nimaltd/master-modbus] GPLv3

[링크 : https://community.st.com/t5/stm32-mcus-products/how-to-implement-modbus-master-on-stm32/td-p/120964]

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Posted by 구차니

SPI NSS, NSSP mode

대충(?) 찾아봐도 약어가 안나오는데

NSSP mode는 NSS Pulse mode 인 것 같고

All SPI interfaces support NSS pulse mode, (STM32H757xI 데이터시트 발췌)

[링크 : https://www.digikey.kr/en/maker/projects/getting-started-with-stm32-how-to-use-spi/09eab3dfe74c4d0391aaaa99b0a8ee17]

NSS는 Negative Slave Select가 아닐까 추정된다.

SCK : Serial Clock. Alternatives:
SCK, SCLK, CLK, SCL

MOSI : "Master" Out → "Slave" In. Now can be read as "Main" Out "Sub" In, or can use these alternatives:
SIMO, MTSR, SPID - correspond to MOSI on both main and sub devices, connects to each other
SDI, DI, DIN, SI, SDA - on sub-only devices; Various abbreviations for "Serial" "Data" "In". Connects to MOSI (or alternative names) on main
SDO, DO, DOUT, SO - on main-only devices; Various abbreviations for "Serial" "Data" "Out". connects to MOSI (or alternative names) on sub
COPI, PICO for "peripheral and controller",[36][37] or COTI for "controller" and "target"[38]

MISO : "Master" In ← "Slave" Out. Now can be read as "Main" In "Sub" Out, or can use these alternatives:
SOMI, MRST, SPIQ - correspond to MISO on both main and sub devices, connects to each other
SDO, DO, DOUT, SO - on sub-only devices; connects to MISO (or alternative names) on main
SDI, DI, DIN, SI - on main-only devices; connects to MISO (or alternative names) on sub
CIPO, POCI,[36][37] or CITO[38]

SS : "Slave" Select (same functionality as Chip Select). Alternatives:
SS, SS, SSEL, NSS, /SS, SS# (sub select)
CS, CS (chip select)
CE (chip enable)

[링크 : https://en.wikipedia.org/wiki/Serial_Peripheral_Interface]

SPI 통신은 크게 4개 모드가 있는데

Clock Polarity 와 Clock Phase의 조합으로 총 4가지가 존재한다.

[링크 : https://en.wikipedia.org/wiki/Serial_Peripheral_Interface]

[링크 : https://igotit.tistory.com/entry/SPI-mode-4%EC%A2%85-CPOL-CPHA]

STM32CubeIDE 에서는

CPOL은 high, low,

CPHA는 1edge , 2edge로 명명되는데

ST32H757xI 메뉴얼에서는 아래와 같이 그려주고 있고

MOSI가 먼저 가면 MISO가 응답오는 식으로 반응하고

읽는 타이밍은 CPHA / CPOL의 폴링 혹은 라이징 엣지에서 읽게 되는데, 앞의 엣지, 뒤의 엣지 식으로 표현되기도 하낟.

CPHA가 lsb로 생각하면 외우기가 좀 쉬우려나?

[링크 : https://igotit.tistory.com/entry/SPI-mode-4종-CPOL-CPHA]

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Posted by 구차니

FDE CIE

디버깅 관련 정보가 들어있는 곳이라는데

NUCLEO-G474RE\Exe\Project.axf: Warning: L6775W: stl_sch_main.o(.debug_frame) has FDEs which use CIEs which are not in this section.

"이 섹션에 존재하지 않는 CIEs를 사용하는 FDEs가 section name에 존재한다." 라고 해석하면 맞나?

L6775W:<objname>(<secname>) has FDEs which use CIEs which are not in this section.

[링크 : https://developer.arm.com/documentation/100074/0613/linker-errors-and-warnings/list-of-the-armlink-error-and-warning-messages]

CIE 는 모든 익셉션 핸들러들이 공통적으로실행하게되는 초반의 바이트코드들을 의미하고
FDE 는 익셉션이 발생한 위치별로 catch 로 가기위해 복구해야하는스택프레임이 달라지는부분이 반영되는 코드들이다.

[링크 : https://daehee87.tistory.com/468]

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Posted by 구차니

code alignement factor?

keil 에서 빌드했더니 왜 1이 나온게 있지?

00000208 0000000c ffffffff CIE
  Version:               1
  Augmentation:          ""
  Code alignment factor: 2
  Data alignment factor: -4
  Return address column: 14

[링크 : https://community.st.com/t5/stm32-mcus-products/code-alignment-questions/td-p/63653]

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구차니의 잡동사니 모음

'embeded/Cortex-M7 STM'에 해당되는 글 36건

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