구차니의 잡동사니 모음

There is no strict definition of these terms, according to the IEEE Std. However, customarily, structural refers to describing a design using module instances (especially for the lower-level building blocks such as AND gates and flip-flops), whereas behavioral refers to describing a design using always blocks.

Gate netlists are always structural, and RTL code is typically behavioral. It is common for RTL to have instances of clock gates and synchronizer cells. 

11. Structural vs. Behavioral Verilog

To clarify the difference between structural and behavioral verilog: 
Structural verilog is composed of module instances and their interconnections (by wires) only.  The use of regs, explicit time delays, arithmetic expressions, procedural assignments, or other verilog control flow structures are considered behavioral verilog.

As stated earlier, your project code will consist primarily of structural verilog.  You will use behavioral statements for debugging purposes only.  In fact, you will probably only instantiate two regs in your whole design: one for the clock and one for a RESET signal that is asserted at the beginning of your simulation.

This section has described all of the Verilog functionality you will need for your final project.   If you want more information on behavioral Verilog, try reading the Bucknell CSCI Verilog Manual or the verilog manual at The University of Edinburgh. 

Example 4

module my_module (a, b, c);

input a, b;

output c;

  assign c = a & b ;

endmodule

module top (a, b, c) ;

input [3:0] a, b;

output [3:0] c;

  my_module inst [3:0] (a, b, c);

endmodule 

genvar k;

generate for (k = 1; k <`wordsize - 1; k = k + 1)

 begin

    I2S_dff instance (.d(sd), .q(q_out[i]), .r(wsp), .en(dec_out[i]), .sck(clk));

    datareg_in = |q_out;

 end

endgenerate 

From Verilog-95 you can have a vector of instances:

d_flipflop ff[7:0] (A, Q, reset clk); 

3. PARALLEL STATEMENTS 

always sequential_statement

5. SEQUENTIAL STATEMENTS

@ (event [{or event}]) sequential_statement

endmodule 

module module_name(module_in_outs);

// 일종의 입출력 변수들 정의(타입은 아직 정의하지 않고 이름만 정의

    // module의 핀(?)에 대한 입출력 방향과 타입을 정의

    input pin_name;

    output pin_name2;

    inout pin_name3;

    // 방향 지시자 없는 내부변수 선언

    wire pin_nam4;

    reg [1:0] count;

    // 행위를 정의함 - structural coding 라고 써있음

    assign out = in;

    // 조사필요

   always@(posedge iCLK or negedge iRSTN)

   submodule sub_module_name

   (

      .sub_module_pin(main_module_pin),

   );

// module의 끝

endmodule