구차니의 잡동사니 모음

2. RO Data are the constants.
Total RAM Size = RW Data + ZI Data
Total ROM Size = Code + RO Data + RW Data

void Timer0A_Handler(void)		// Timer0A - internal timer
{
	TimerIntClear(TIMER0_BASE, TIMER_TIMA_TIMEOUT);

	count_10ms++;

	if ((count_10ms + 75) %  100 == 0)		{TimeService_100ms();}
	if ((count_10ms +  1) %  250 == 0)		{TimeService_250ms();}
	if ((count_10ms + 50) %  500 == 0)		{TimeService_500ms();}
	if ((count_10ms + 25) % 1000 == 0)		{TimeService_1000ms();	count_10ms = 0;}
}

static void SetRTCFucntion(void)
{
//	time_t current_time;
//	struct tm struct_time = { 0, 0, 10, 26,2,2012 - 1900,0,0,0};
//	current_time = mktime(&struct_time);
	
	SysCtlPeripheralEnable(SYSCTL_PERIPH_HIBERNATE);
		HibernateEnableExpClk(SysCtlClockGet());
		HibernateClockSelect(HIBERNATE_CLOCK_SEL_DIV128);
		HibernateRTCEnable();
//		HibernateRTCSet(current_time);
		HibernateWakeSet(HIBERNATE_WAKE_PIN);
		HibernateRequest();
}

• nSRST bi-directional (open collector)
  This pin serves two purposes. It can be used by the adapter to reset the target board, which is most useful during remote debugging. Furthermore, the adapter is able to detect that the reset is triggered on the target by another event, like pressing the reset button or a watchdog timeout.
• nTRST from adapter to target
  According to the JTAG standard, the TAP controller is reset to a known state by keeping TMS high for five consecutive TCK cycles. However, some targets have problems with this sequence and thus require a hardware reset, which is marked optional in the IEEE specification. On several chips, like the AT91R40008 used on Ethernut 3, nSRST and nTRST are internally tied together. The disadvantage with this design is, that you can’t trigger a breakpoint immediately after a target hardware reset. If this signal is not used on the target, it is recommended to pull up this line with 10kOhm.