큭... VHDL 공부 하는데 Verilog 라니.. 비겁하다!!!
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// ============================================================================
// Copyright (c) 2011 by Terasic Technologies Inc.
// ============================================================================
//
// Permission:
//
// Terasic grants permission to use and modify this code for use
// in synthesis for all Terasic Development Boards and Altera Development
// Kits made by Terasic. Other use of this code, including the selling
// ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Terasic provides no warranty regarding the use
// or functionality of this code.
//
// ============================================================================
//
// Terasic Technologies Inc
// 356 Fu-Shin E. Rd Sec. 1. JhuBei City,
// HsinChu County, Taiwan
// 302
//
// web: http://www.terasic.com/
// email: support@terasic.com
//
// ============================================================================
// Major Functions/Design Description:
//
// Please refer to DE0_Nano_User_manual.pdf in DE0_Nano system CD.
//
// ============================================================================
// Revision History:
// ============================================================================
// Ver.: |Author: |Mod. Date: |Changes Made:
// V1.0 |EricChen |02/01/2011 |
// ============================================================================
//=======================================================
// This code is generated by Terasic System Builder
//=======================================================
module DE0_NANO(
//////////// CLOCK //////////
CLOCK_50,
//////////// LED //////////
LED,
//////////// KEY //////////
KEY,
//////////// SW //////////
SW,
//////////// SDRAM //////////
DRAM_ADDR,
DRAM_BA,
DRAM_CAS_N,
DRAM_CKE,
DRAM_CLK,
DRAM_CS_N,
DRAM_DQ,
DRAM_DQM,
DRAM_RAS_N,
DRAM_WE_N,
//////////// EPCS //////////
EPCS_ASDO,
EPCS_DATA0,
EPCS_DCLK,
EPCS_NCSO,
//////////// Accelerometer and EEPROM //////////
G_SENSOR_CS_N,
G_SENSOR_INT,
I2C_SCLK,
I2C_SDAT,
//////////// ADC //////////
ADC_CS_N,
ADC_SADDR,
ADC_SCLK,
ADC_SDAT,
//////////// 2x13 GPIO Header //////////
GPIO_2,
GPIO_2_IN,
//////////// GPIO_0, GPIO_0 connect to GPIO Default //////////
GPIO_0_D,
GPIO_0_IN,
//////////// GPIO_0, GPIO_1 connect to GPIO Default //////////
GPIO_1_D,
GPIO_1_IN,
);
//=======================================================
// PARAMETER declarations
//=======================================================
//=======================================================
// PORT declarations
//=======================================================
//////////// CLOCK //////////
input CLOCK_50;
//////////// LED //////////
output [7:0] LED;
//////////// KEY //////////
input [1:0] KEY;
//////////// SW //////////
input [3:0] SW;
//////////// SDRAM //////////
output [12:0] DRAM_ADDR;
output [1:0] DRAM_BA;
output DRAM_CAS_N;
output DRAM_CKE;
output DRAM_CLK;
output DRAM_CS_N;
inout [15:0] DRAM_DQ;
output [1:0] DRAM_DQM;
output DRAM_RAS_N;
output DRAM_WE_N;
//////////// EPCS //////////
output EPCS_ASDO;
input EPCS_DATA0;
output EPCS_DCLK;
output EPCS_NCSO;
//////////// Accelerometer and EEPROM //////////
output G_SENSOR_CS_N;
input G_SENSOR_INT;
output I2C_SCLK;
inout I2C_SDAT;
//////////// ADC //////////
output ADC_CS_N;
output ADC_SADDR;
output ADC_SCLK;
input ADC_SDAT;
//////////// 2x13 GPIO Header //////////
inout [12:0] GPIO_2;
input [2:0] GPIO_2_IN;
//////////// GPIO_0, GPIO_0 connect to GPIO Default //////////
inout [33:0] GPIO_0_D;
input [1:0] GPIO_0_IN;
//////////// GPIO_0, GPIO_1 connect to GPIO Default //////////
inout [33:0] GPIO_1_D;
input [1:0] GPIO_1_IN;
//=======================================================
// REG/WIRE declarations
//=======================================================
wire reset_n;
reg [26:0] counter;
reg [5:0] PWM_adj;
reg [6:0] PWM_width;
reg [7:0] LED;
//=======================================================
// Structural coding
//=======================================================
assign reset_n = KEY[0];
always @(posedge CLOCK_50 or negedge reset_n)
begin
if(!reset_n)
begin
counter <= 0;
LED[0] <= 0;
end
else begin
counter <= counter+1;
PWM_width <= PWM_width[5:0]+ PWM_adj;
if(counter[26])
begin
PWM_adj <= counter[25:20];
end
else begin
PWM_adj <= ~ counter[25:20];
end
LED[0] <= ~PWM_width[6];
LED[1] <= ~PWM_width[6];
LED[2] <= ~PWM_width[6];
LED[3] <= ~PWM_width[6];
LED[4] <= PWM_width[6];
LED[5] <= PWM_width[6];
LED[6] <= PWM_width[6];
LED[7] <= PWM_width[6];
end
end
endmodule |
일단.. 눈에 들어오는 키워드는
begin - end 구조 동일해 보이고..
postedge CLOCK_50 으로 50Mhz OSC입력을 positive edge 니까.. rising edge일려나?
negedge reset_n 이니까.. KEY_0를 RESET_N으로 맵핑했고(작동이 그러니까..)
그게 falling edge로 잡히면 트리거 되서 작동하는데
!reset_n이면 카운터와 LED[0]을 0으로 각각 셋팅(LED 0번만 끄고 counter를 0으로 설정)
reset_n이면
카운터(27비트 = 134,217,728)를 증가하면서 PWM_Width 값을 더해주는데
카운터의 MSB가 1이 되면 (67,108,864 초과) counter의 25~20번째 비트를 복사하고
0이면 counter의 25~20번째 비트를 negate 시켜서 (그러니까 감소) 복사한다.
그래서 LED[0:7] 에 PWM_width를 입력해 주는데
가장 상위 비트만 출력함으로서
0과 1을 50Mhz에 연동해서 빠르게 on/off 함으로서 PWM을 구현하게 되는건가?
+
posedge means the transition from 0 to 1
negedge the oposit transition from 1 to 0
그러니까.. posedge는 rising edge고, negedge는 falling edge가 맞겠네?
[링크 : http://www.alteraforum.com/forum/showthread.php?t=19611]
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