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GENERAL: MERGING TWO APPLICATIONS INTO ONE INTEL HEX FILE

Information in this article applies to:

C51 All Versions

C166 All Versions

C251 All Versions

MDK-ARM any Version 

srec_cat.exe HexFile1.hex -Intel HexFile2.hex -Intel -o MergedHexFile.hex -Intel

CMSIS Drivers No CMSIS-Driver in Device Family Pack.

CMSIS-RTOS Blinky     EK-TM4C1294XL

CMSIS-RTOS Blinky     DK-TM4C129x 

Description

CMSIS provides additional debug functions to enlarge the Debug Access. Data can be transmitted via a certain global buffer variable towards the target system.

The Cortex-M3 / Cortex-M4 / Cortex-M7 incorporates the Instrumented Trace Macrocell (ITM) that provides together with the Serial Viewer Output (SVO) trace capabilities for the microcontroller system. The ITM has 32 communication channels; two ITM communication channels are used by CMSIS to output the following information:

ITM Channel 0: implements the ITM_SendChar function which can be used for printf-style output via the debug interface.

ITM Channel 31: is reserved for the RTOS kernel and can be used for kernel awareness debugging. 

;******************************************************************************

;

; The reset handler, which gets called when the processor starts.

;

;******************************************************************************

    export  Reset_Handler

Reset_Handler

    ;

    ; Initialize the processor.

    ;

    bl      ProcessorInit

    ;

    ; Branch to the SRAM copy of the reset handler.

    ;

    ldr     pc, =Reset_Handler_In_SRAM

;******************************************************************************

;

; Initialize the processor by copying the boot loader from flash to SRAM, zero

; filling the .bss section, and moving the vector table to the beginning of

; SRAM.  The return address is modified to point to the SRAM copy of the boot

; loader instead of the flash copy, resulting in a branch to the copy now in

; SRAM.

;

;******************************************************************************

    export  ProcessorInit

ProcessorInit

    ;

    ; Copy the code image from flash to SRAM.

    ;

    if      :def:_FLASH_PATCH_COMPATIBLE

    movs    r0, #0x1000

    else

    movs    r0, #0x0000

    endif

    movs    r1, #0x0000

    movt    r1, #0x2000

    import  ||Image$$SRAM$$ZI$$Base||

    ldr     r2, =||Image$$SRAM$$ZI$$Base||

copy_loop

        ldr     r3, [r0], #4

        str     r3, [r1], #4

        cmp     r1, r2

        blt     copy_loop

    ;

    ; Zero fill the .bss section.

    ;

    movs    r0, #0x0000

    import  ||Image$$SRAM$$ZI$$Limit||

    ldr     r2, =||Image$$SRAM$$ZI$$Limit||

zero_loop

        str     r0, [r1], #4

        cmp     r1, r2

        blt     zero_loop

    ;

    ; Set the vector table pointer to the beginning of SRAM.

    ;

    movw    r0, #(NVIC_VTABLE & 0xffff)

    movt    r0, #(NVIC_VTABLE >> 16)

    movs    r1, #0x0000

    movt    r1, #0x2000

    str     r1, [r0]

    ;

    ; Return to the caller.

    ;

    bx      lr