구차니의 잡동사니 모음

//#include <stdio.h>

/*

 * hello.c

 */

int main(void) {

// printf("Hello World!\n");

return 0;

} 

char * const a;

means that the pointer is constant and immutable but the pointed data is not.

You could use const_cast(in C++) or c-style cast to cast away the constness in this case as data itself is not constant.

const char * a;

means that the pointed data cannot be written to using the pointer a. Using a const_cast(C++) or c-style cast to cast away the constness in this case causes Undefined Behavior. 

module dff (clk, d, q);

input clk, d;
output q;
reg q;
always @(posedge clk) q = d;
endmodule
 
module top;
reg data, clock;
wire q_out, net_1;
  dff inst_1 (.d(data), .q(net_1), .clk(clock));
  dff inst_2 (.clk(clock), .d(net_1), .q(q_out));
endmodule

module dff (clk, d, q);

input clk, d;
output q;
reg q;
always @(posedge clk) q = d;
endmodule
 
module top;
reg data, clock;
wire q_out, net_1;
  dff inst_1 (clock, data, net_1);
  dff inst_2 (clock, net_1, q_out);
endmodule

example 1

module dff (clk, d, q);
input clk, d;
output q;
reg q;
always @(posedge clk) q = d;
endmodule
 
module top;
reg data, clock;
wire q_out, net_1;
  dff inst_1 (.d(data), .q(net_1), .clk(clock));
  dff inst_2 (.clk(clock), .d(net_1), .q(q_out));
endmodule

In the top module there are two instantiations of the 'dff' module. In both cases port connections are done by name, so the port order is insignificant. The first port is input port 'd', the second is output 'q' and the last is the clock in the 'inst_1'. In the dff module the order of ports is different than either of the two instantiations.

Example 2

module dff (clk, d, q);
input clk, d;
output q;
reg q;
always @(posedge clk) q = d;
endmodule
 
module top;
reg data, clock;
wire q_out, net_1;
  dff inst_1 (clock, data, net_1);
  dff inst_2 (clock, net_1, q_out);
endmodule

Example 3

dff inst_1 (clock, , net_1);

Second port is unconnected and has the value Z because it is of the net type.

Example 4

module my_module (a, b, c);
input a, b;
output c;
  assign c = a & b ;
endmodule
 
module top (a, b, c) ;
input [3:0] a, b;
output [3:0] c;
  my_module inst [3:0] (a, b, c);

endmodule 

module DE0_NANO(

input CLOCK_50

);

endmodule

module DE0_NANO(

CLOCK_50

);

input           CLOCK_50;

endmodule

Gate Level Modeling

- primitives 를 이용한 게이트 레벨 설계방법

- and, or, nand, nor, xor, xnor

- buf, not

- bufif1, bufif0, notif1, notif0 (tri-state)

module and_from_nand(X, Y, F);

input X, Y;

output F;

wire W;

// Two instantiations of the module NAND

nand U1(W, X, Y);

nand U2(F, W, W);

endmodule 

Dataflow Modeling 

- assign 키워드 사용

- net에 특정 논리값을 지정함으로서 데이터의 흐름을 통해(routing?) 회로 구성

- 각종 연산자들 사용가능

wire out = in1 & in2 ;

wire out;

assign out = in1 & in2 ; 

Behavioral Modeling 

- always 키워드 이용

- always 내부의 내용은 시퀀셜 하게 작동. always들 끼리는 병렬로 작동

- alwyas 는 항상 작동하므로, 절차적 언어의 무한반복문과 유사한 개념

- 절차적(always) 에서는 블러킹과 넌블러킹이 존재

(즉, dataflow나 gate level에서는 해당 개념이 존재하지 않음. 이녀석이 혼동의 원인)

- 블러킹 '=' 라인 순서대로 수행

- 넌블러킹 '<=' 넌블러킹 끼리는 동시 수행

- C언어 같은 느낌으로 if, switch-case등을 지원

- for 문은 합성툴에 따라 반복횟수 제한되거나, 지원하지 않음

// illustration 1 : blocking

always @(posegde clk)

a = b ;

always @(posedge clk)

b = a;

// illustration 2 : nonblocking

always @(posegde clk)

a <= b ;

always @(posedge clk)

b <= a; 

reg [3:0]  r_VAL_1 = 4'b0111;

reg [3:0]  r_VAL_2 = 4'b1100;

wire [7:0] w_CAT;

assign w_CAT = {r_VAL_1, r_VAL_2}; 

reg [3:0]  r_VAL_1 = 4'b0111;

{3{r_VAL_1}};

# Replication of 0x7, 3 times is 0x777

reg r_C;

&4'b1101;

r_C = |4'b0010;

reg r_A = 1'b1;

reg r_B = 1'b0;

assign w_AND_SCALAR = r_A & r_B;

There is no strict definition of these terms, according to the IEEE Std. However, customarily, structural refers to describing a design using module instances (especially for the lower-level building blocks such as AND gates and flip-flops), whereas behavioral refers to describing a design using always blocks.

Gate netlists are always structural, and RTL code is typically behavioral. It is common for RTL to have instances of clock gates and synchronizer cells. 

11. Structural vs. Behavioral Verilog

To clarify the difference between structural and behavioral verilog: 
Structural verilog is composed of module instances and their interconnections (by wires) only.  The use of regs, explicit time delays, arithmetic expressions, procedural assignments, or other verilog control flow structures are considered behavioral verilog.

As stated earlier, your project code will consist primarily of structural verilog.  You will use behavioral statements for debugging purposes only.  In fact, you will probably only instantiate two regs in your whole design: one for the clock and one for a RESET signal that is asserted at the beginning of your simulation.

This section has described all of the Verilog functionality you will need for your final project.   If you want more information on behavioral Verilog, try reading the Bucknell CSCI Verilog Manual or the verilog manual at The University of Edinburgh.