example 1 module dff (clk, d, q); input clk, d; output q; reg q; always @(posedge clk) q = d; endmodule module top; reg data, clock; wire q_out, net_1; dff inst_1 (.d(data), .q(net_1), .clk(clock)); dff inst_2 (.clk(clock), .d(net_1), .q(q_out)); endmodule In the top module there are two instantiations of the 'dff' module. In both cases port connections are done by name, so the port order is insignificant. The first port is input port 'd', the second is output 'q' and the last is the clock in the 'inst_1'. In the dff module the order of ports is different than either of the two instantiations. Example 2 module dff (clk, d, q); input clk, d; output q; reg q; always @(posedge clk) q = d; endmodule module top; reg data, clock; wire q_out, net_1; dff inst_1 (clock, data, net_1); dff inst_2 (clock, net_1, q_out); endmodule Example 3 dff inst_1 (clock, , net_1); Second port is unconnected and has the value Z because it is of the net type. Example 4 module my_module (a, b, c); input a, b; output c; assign c = a & b ; endmodule module top (a, b, c) ; input [3:0] a, b; output [3:0] c; my_module inst [3:0] (a, b, c);
endmodule |