Tynuxbox SDRAM 초기화 관련 내용

문서상에 두개의 레지스터 값이 있으니 한번 시도는 해봐야겠다 ㅋ

MDCNFG 0000 0000 0000 0000 0000 1001 1010 1001
  DLATCH0 - 1 - Return Data from SDRAM latching scheme for pair 0/1 > 1 – Latch return data with return clock
  DTC0 - 01 - Timing Category for SDRAM pair 0/1 > 00 - tRP=2clks, CL=2, tRCD=1clks, tRAS(min)=3clks, tRC=4clks
  DNB0 - 1 - Number of banks in lower partition pair > 0 – 2 internal SDRAM banks
  DRAC0 - 01 - SDRAM row address bit count for partition pair 0/1 > 01 – 12 row address bits
  DCAC0 - 01 - Number of Column Address bits for partition pair 0/1 > 01 - 9 column address bits
  DWID0 - 0 - SDRAM data bus width for partition pair 0/1 > 0 – 32 bits 

  DE0 - 1 - SDRAM enable for partition 0 > 1 – SDRAM partition enabled

MDREFR 0000 0000 0000 1111 1111 0000 0010 0111
  APD - 1 - SDRAM/Synchronous Static Memory Auto-Power-Down Enable.
  K2DB2 - 1 - SDRAM Clock Pin 2 (SDCLK2) Divide by 2 Control/Status
                   1 – SDCLK2 runs at one-half the MEMCLK frequency

  K2RUN - 1 - SDRAM Clock Pin 2 (SDCLK<2>) Run Control/Status
                   1 – SDCLK2 enabled
  K1DB2 - 1 - SDRAM Clock Pin 1 (SDCLK1) Divide by 2 Control/Status
                    1 – SDCLK1 runs at one-half the MEMCLK frequency
  K1RUN - 1 - SDRAM Clock Pin 1 (SDCLK<1>) Run Control/Status
                    1 – SDCLK1 enabled
  E1PIN - 1 - SDRAM Clock Enable Pin 1 (SDCKE1) Level Control/Status
                    1 – SDCKE1 is enabled
  K0DB2 - 1 - Synchronous Static Memory Clock Pin 0 (SDCLK<0>) Divide by 2 Control/Status
                    1 – SDCLK0 runs at one-half the memory clock frequency
  K0RUN - 1 - Synchronous Static Memory Clock Run Pin 0 (SDCLK<0>) Control/Status

                    1 – SDCLK0 is enabled
  E0PIN - 1 - Synchronous Static Memory Clock Enable Pin 0 (SDCKE<0>) Level Control/Status
                    1 – SDCKE0 is enabled
  DRI - 0000 0010 0111 - SDRAM refresh interval, all partitions.
                    DRI = (Number of memclk cycles-31) / 32 = (Refresh time / rows) x Memory clock frequency / 32.