구차니의 잡동사니 모음

module halfadder(a,b,s,c);

input a,b;

output s,c;

xor(s,a,b);

and(c,a,b);

endmodule 

vsim halfadder

# vsim halfadder 

# Start time: 14:44:03 on Mar 19,2018

# Loading work.halfadder

view wave

# .main_pane.wave.interior.cs.body.pw.wf

add wave *

force a 0 0ns, 1 20ns -r 40ns

run 100ns 

The Video and Image Processing Suite contains the following MegaCore® functions:

■ “2D FIR Filter MegaCore Function” on page 4–1

■ “2D Median Filter MegaCore Function” on page 5–1

■ “Alpha Blending MegaCore Function” on page 6–1

■ “Avalon-ST Video Monitor MegaCore Function” on page 7–1

■ “Chroma Resampler MegaCore Function” on page 8–1

■ “Clipper MegaCore Function” on page 9–1

■ “Clipper II MegaCore Function” on page 10–1

■ “Clocked Video Input MegaCore Function” on page 11–1

■ “Clocked Video Output MegaCore Function” on page 12–1

■ “Color Plane Sequencer MegaCore Function” on page 13–1

■ “Color Space Converter MegaCore Function” on page 14–1

■ “Control Synchronizer MegaCore Function” on page 15–1

■ “Deinterlacer MegaCore Function” on page 16–1

■ “Deinterlacer II MegaCore Function” on page 17–1

■ “Broadcast Deinterlacer MegaCore Function” on page 18–1

■ “Frame Reader MegaCore Function” on page 19–1

■ “Frame Buffer MegaCore Function” on page 20–1

■ “Gamma Corrector MegaCore Function” on page 21–1

■ “Interlacer MegaCore Function” on page 22–1

■ “Scaler II MegaCore Function” on page 23–1

■ “Switch MegaCore Function” on page 24–1

■ “Test Pattern Generator MegaCore Function” on page 25–1

■ “Trace System MegaCore Function” on page 26–1

• UltraScale+ GTR (6.0 Gb/s): Easiest integration of common protocols to the Zynq Processor Subsystem
• UltraScale+ GTH (16.3 Gb/s): Low power & high performance for the toughest backplanes
• UltraScale+ GTY (32.75 Gb/s): Maximum NRZ performance for the fastest optical and backplane applications; 33G transceivers for chip-to-chip, chip-to-optics, and 28G backplanes
• UltraScale GTH (16.3 Gb/s): Low power & high performance for the toughest backplanes
• UltraScale GTY (30.5 Gb/s): High performance for optical and backplane applications; 30G transceivers for chip-to-chip, chip-to-optics, and 28G backplanes
• UltraScale+ GTM (58 Gb/s): Maximum performance using PAM4 for 58G chip-to-chip, chip-to-optics, and backplane applications
• 7 Series GTP (6.6 Gb/s): Power optimized transceiver for consumer and legacy serial standards
• 7 Series GTX (12.5 Gb/s): Lowest jitter and strongest equalization in a mid-range transceiver
• 7 Series GTH (13.1 Gb/s): Backplane and optical performance through world class jitter and equalization
• 7 Series GTZ (28.05 Gb/s): Highest rate, lowest jitter 28G transceiver in a 28nm FPGA
• Spartan-6 GTP (3.2 Gb/s): Power and cost optimized transceiver for cost-sensitive applications

sld_virtual_jtag sld_virtual_jtag_component (

.ir_out (ir_out),

.tdo (tdo),

.virtual_state_cir (sub_wire0),

.virtual_state_pdr (sub_wire1),

.ir_in (sub_wire2),

.tdi (sub_wire3),

.virtual_state_udr (sub_wire4),

.tck (sub_wire5),

.virtual_state_e1dr (sub_wire6),

.virtual_state_uir (sub_wire7),

.virtual_state_cdr (sub_wire8),

.virtual_state_e2dr (sub_wire9),

.virtual_state_sdr (sub_wire10)

// synopsys translate_off

,

.jtag_state_cdr (),

.jtag_state_cir (),

.jtag_state_e1dr (),

.jtag_state_e1ir (),

.jtag_state_e2dr (),

.jtag_state_e2ir (),

.jtag_state_pdr (),

.jtag_state_pir (),

.jtag_state_rti (),

.jtag_state_sdr (),

.jtag_state_sdrs (),

.jtag_state_sir (),

.jtag_state_sirs (),

.jtag_state_tlr (),

.jtag_state_udr (),

.jtag_state_uir (),

.tms ()

// synopsys translate_on

);