갑자기 little endian인 x86 시스템에서
어떤식으로 Shift 연산자가 작동하는지 멘붕..
엔디안은 메모리에 저장하는 것이기에..
혹시 레지스터는 빅 엔디안으로 구현되는건가?
근데 수업 시간 기억으로는.. little endian이라 자릿수 늘어나도 처리가 부담없다고
그렇게 배운거 봐서는 adder도 모두 little endian인거 같긴한데..
블랙박스 부분이라 알수가 없네..
아무튼.. C 언어 레벨에서는 논리적으로는 big endian으로 처리하고
변환할 때 반대로 구현해줄줄 알았는데 그것도 아니고..(그냥 right는 SAR SHR로 구현)
도대체 어떻게 처리하는건지 알수가 없다.. ㅠㅠ
[링크 : https://code.i-harness.com/ko/q/5c375b]
[링크 : https://www.joinc.co.kr/w/Site/Network_Programing/Documents/endian]
[링크 : https://msdn.microsoft.com/ko-kr/library/336xbhcz.aspx?f=255&MSPPError=-2147217396]
[링크 : https://blogs.msdn.microsoft.com/.../hello-arm-exploring-undefined-unspecified-and-implementation-defined-behavior-in-c/]
[링크 : https://stackoverflow.com/questions/7184789/does-bit-shift-depend-on-endianness]
[링크 : https://stackoverflow.com/questions/1041554/bitwise-operators-and-endianness/1041573]
[링크 : https://www.ibm.com/developerworks/aix/library/au-endianc/index.html]
1235 page
Description Shifts the bits in the first operand (destination operand) to the left or right by the number of bits specified in the
second operand (count operand). Bits shifted beyond the destination operand boundary are first shifted into the CF
flag, then discarded. At the end of the shift operation, the CF flag contains the last bit shifted out of the destination
operand.
The destination operand can be a register or a memory location. The count operand can be an immediate value or
the CL register. The count is masked to 5 bits (or 6 bits if in 64-bit mode and REX.W is used). The count range is
limited to 0 to 31 (or 63 if 64-bit mode and REX.W is used). A special opcode encoding is provided for a count of 1.
The shift arithmetic left (SAL) and shift logical left (SHL) instructions perform the same operation; they shift the
bits in the destination operand to the left (toward more significant bit locations). For each shift count, the most
significant bit of the destination operand is shifted into the CF flag, and the least significant bit is cleared (see
Figure 7-7 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1). The shift arithmetic right (SAR) and shift logical right (SHR) instructions shift the bits of the destination operand to
the right (toward less significant bit locations). For each shift count, the least significant bit of the destination
operand is shifted into the CF flag, and the most significant bit is either set or cleared depending on the instruction
type. The SHR instruction clears the most significant bit (see Figure 7-8 in the Intel® 64 and IA-32 Architectures
Software Developer’s Manual, Volume 1); the SAR instruction sets or clears the most significant bit to correspond
to the sign (most significant bit) of the original value in the destination operand. In effect, the SAR instruction fills
the empty bit position’s shifted value with the sign of the unshifted value (see Figure 7-9 in the Intel® 64 and IA-32
Architectures Software Developer’s Manual, Volume 1). |
[링크 : https://www.intel.com/.../64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf]
case 4: packet[4] = (val >> 24) & 0xFF; 0115687B mov ebx,ecx 0115687D sar ebx,18h 01156880 mov byte ptr [edi+4],bl packet[5] = (val >> 16) & 0xFF; 01156883 mov ebx,ecx 01156885 sar ebx,10h 01156888 mov byte ptr [edi+5],bl packet[6] = (val >> 8) & 0xFF; 0115688B mov ebx,ecx 0115688D sar ebx,8 01156890 mov byte ptr [edi+6],bl packet[7] = (val) & 0xFF; 01156893 mov byte ptr [edi+7],cl break; 01156896 jmp $LN11+54h (11568A8h) break; |
흐음... 어렵다...