timequest time analyzer?

책에서 본거 처럼(구버전 기준이긴 했지만)

최대 작동 클럭이 rpm 미터 처럼 똭 뜨지 않아서 찾아 보는중

timequest는 구버전에서의 time analzyer의 상품명(?) 이런건가?

The TimeQuest timing analyzer is a powerful ASIC-style timing analysis tool that validates the timing performance of all logic in a design using industry standard constraint, analysis, and reporting methodology  Synopsis Design Constraints (SDC) tool command language (Tcl)

[링크 : https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/manual/mnl_sdctmq.pdf]

먼가 찾아서 막 누르다 보니 이런게 나오네 -ㅁ-?

[링크 : ftp://ftp.altera.com/up/pub/Intel_Material/15.1/Tutorials/VHDL/Timequest.pdf]

[링크 : https://www.altera.com/en_US/pdfs/literature/ug/ug_tq_tutorial.pdf]

암튼 현재로서는 Timing Analyzer로만 표기가 된다.

컴파일 하다 보면 아래와 같은 Timing Analyzer 항목이 보이는데

타이밍 모델은 온도에 따른 작동 속도가 있고

speed grade별로 시뮬레이션을 하는데 영향을 주는 요소인 것으로 보인다.

speed grade / supply voltage / junction temperature

Intel FPGAs must operate in a continuum of conditions.   These conditions include the die junction temperature, which varies depending upon the design's requirements. Commercial parts have a legal range of 0°C to 85°C and industrial parts have a legal range of -40°C to 100°C. There are even wider temperature ranges, such as those for automotive and military devices.   Another aspect of the operating conditions is the voltage supply levels. The most critical voltages for maintaining FPGA performance is the Vcc and the various I/O supplies. Each of the supply voltages has a legal operating range. For example, a subset of Stratix® IV FPGAs has a valid Vcc range of 0.87 V to 0.93 V.   The third aspect of the operating conditions is the relative speed of each FPGA versus the limit of the speed grade with which it is marked. This is one aspect that the designer has no control over. It should also be noted that devices within one speed grade can still differ slightly in performance, predominantly due to variation in the manufacturing process. All devices, however, are guaranteed to be faster than the limit of the speed grade.

[링크 : https://www.altera.com/en_US/pdfs/literature/wp/wp-01139-timing-model.pdf]