openRISC OR1k(1000) OR1200

The OR1200 is a 32-bit scalar RISC with Harvard microarchitecture, 5 stage integer pipeline, virtual memory support (MMU) and basic DSP capabilities.

[링크 : http://opencores.org/or1k/OR1200_OpenRISC_Processor]

CPU CPUID

or1ksim 0x00

OR1200 0x12

mor1kx 0x01

AltOr32 0x32

OR10 0x10

or1knd i5 0xd5

[링크 : http://opencores.org/or1k/OR1K_CPU_Cores]

=== CPUID관련 ===

For now, we have implemented a CPU-ID register, that is SPR_SYS register 9, to allow different stacks in the same memory etc. 

[링크 : http://opencores.com/forum,OpenRISC,0,3666]

    Section 15.2

    Version Register (VR)

    The version register is a 32-bit special-purpose supervisor-level

register accessible with the l.mfspr instruction.

    It identifies the implementation (model) and version of the

OpenRISC 1000 processor.

    [31:24] VER Version

    Implementation-specific version information. This value should

increase for more recent versions. The CPU implementation

specification document should indicate how to interpret this field.

    [23:0] CPUID CPU Identification

    Implementation-specific identification number. Each unique

implementation should have a unique identification value.

[링크 : http://lists.opencores.org/pipermail/openrisc/2011-August/000090.html]

>>> +++ b/newlib/libc/machine/or1k/include/spr-defs.h

>>> @@ -201,6 +201,15 @@

>>>  #define SPR_VR2_CPUID_OFF   24

>>>  #define SPR_VR2_VER_OFF     0

>>>

>>> +/*

>>> + * CPU implementation unique identifiers

>>> + */

>>> +#define SPR_VR2_CPUID_OR1KSIM   0x00

>>> +#define SPR_VR2_CPUID_MOR1KX    0x01

>>> +#define SPR_VR2_CPUID_OR1200    0x12

>>> +#define SPR_VR2_CPUID_ALTOR32   0x32

>>> +#define SPR_VR2_CPUID_OR10      0x10

>>> +

[링크 : http://lists.opencores.org/pipermail/openrisc/2012-December/001171.html]

흐음... 0x13은 머지....

CPU0 : SPR_VR : 0x13000008 CPU1 : SPR_VR : 0x12000008 dprintf("CPU0 : SPR_VR : 0x%X\n", mfspr(SPR_VR)); #define SPR_VR (SPRGROUP_SYS + 0) /*  * Bit definitions for the Version Register  *  */ #define SPR_VR_VER 0xff000000  /* Processor version */ #define SPR_VR_CFG 0x00ff0000  /* Processor configuration */ #define SPR_VR_RES 0x0000ffc0  /* Reserved */ #define SPR_VR_REV 0x0000003f  /* Processor revision */ #define SPR_VR_VER_OFF 24 #define SPR_VR_CFG_OFF 16 #define SPR_VR_REV_OFF 0