구차니의 잡동사니 모음

Info: 2018. 2. 3 오후 1:47:39 - (정보) elf2flash: args = --input=D:/Download/DE0_NANO/software/hello_world_0/hello_world_0.elf --output=D:/Download/DE0_NANO/software/hello_world_0_bsp/flash/hello_world_0_epcs_flash_controller_0.flash --epcs --verbose

Info: 2018. 2. 3 오후 1:47:39 - (미세) elf2flash: Starting

Info: 2018. 2. 3 오후 1:47:39 - (보다 미세) elf2flash: Program Record: 3964 bytes destined for 0x4008000

Info: 2018. 2. 3 오후 1:47:39 - (보다 미세) elf2flash: Program Record: 724 bytes destined for 0x4009250

Info: 2018. 2. 3 오후 1:47:39 - (보다 미세) elf2flash: Start Record: 4008020

Info: 2018. 2. 3 오후 1:47:39 - (미세) elf2flash: Done

Info: Using cable "USB-Blaster [USB-0]", device 1, instance 0x00

Info: Resetting and pausing target processor: 

Info: OK

Info: Reading System ID at address 0x04012030: 

Info: verified

Info: Processor data bus width is 32 bits

Info: Looking for EPCS registers at address 0x04011000 (with 32bit alignment)

Info:   Initial values: 0001703A 04C00074 9801483A 9CFFF804 983FFD1E 0000203A

Info:   Not here: reserved fields are non-zero

Info: Looking for EPCS registers at address 0x04011100 (with 32bit alignment)

Info:   Initial values: 93000237 6300080C 603FFD26 90000335 A8000C26 03010004

Info:   Not here: reserved fields are non-zero

Info: Looking for EPCS registers at address 0x04011200 (with 32bit alignment)

Info:   Initial values: 02C02004 002EE03A 00000F06 90000335 4000683A 0017883A

Info:   Not here: reserved fields are non-zero

Info: Looking for EPCS registers at address 0x04011300 (with 32bit alignment)

Info:   Initial values: 003FD006 5280040C 501496FA 701CD07A 729CB03A 843FFFC4

Info:   Not here: reserved fields are non-zero

Info: Looking for EPCS registers at address 0x04011400 (with 32bit alignment)

Info:   Initial values: 00000000 00000000 00000260 00000000 00000000 00000001

Info:   Valid registers found

Info: EPCS signature is 0x16

Info: EPCS identifier is 0x010216

Info: Leaving target processor paused

Error: No EPCS layout data - looking for section [EPCS-010216]

Error: Unable to use EPCS device

Error: Error code: 8 for command: nios2-flash-programmer "D:/Download/DE0_NANO/software/hello_world_0_bsp/flash/hello_world_0_epcs_flash_controller_0.flash" --base=0x4011000 --epcs --sidp=0x4012030 --id=0x0 --timestamp=1517632677 --device=1 --instance=0 '--cable=USB-Blaster on localhost [USB-0]' --program --verbose 

Info: 2018. 2. 3 오후 1:47:52 - (정보) elf2flash: args = --input=D:/Download/DE0_NANO/software/hello_world_0/hello_world_0.elf --output=D:/Download/DE0_NANO/software/hello_world_0_bsp/flash/hello_world_0_epcs_flash_controller_0.flash --epcs --verbose

Info: 2018. 2. 3 오후 1:47:52 - (미세) elf2flash: Starting

Info: 2018. 2. 3 오후 1:47:52 - (보다 미세) elf2flash: Program Record: 3964 bytes destined for 0x4008000

Info: 2018. 2. 3 오후 1:47:52 - (보다 미세) elf2flash: Program Record: 724 bytes destined for 0x4009250

Info: 2018. 2. 3 오후 1:47:52 - (보다 미세) elf2flash: Start Record: 4008020

Info: 2018. 2. 3 오후 1:47:52 - (미세) elf2flash: Done

Info: Using cable "USB-Blaster [USB-0]", device 1, instance 0x00

Info: Resetting and pausing target processor: 

Info: OK

Info: Reading System ID at address 0x04012030: 

Info: verified

Info: Processor data bus width is 32 bits

Info: Looking for EPCS registers at address 0x04011000 (with 32bit alignment)

Info:   Initial values: 0001703A 04C00074 9801483A 9CFFF804 983FFD1E 0000203A

Info:   Not here: reserved fields are non-zero

Info: Looking for EPCS registers at address 0x04011100 (with 32bit alignment)

Info:   Initial values: 93000237 6300080C 603FFD26 90000335 A8000C26 03010004

Info:   Not here: reserved fields are non-zero

Info: Looking for EPCS registers at address 0x04011200 (with 32bit alignment)

Info:   Initial values: 02C02004 002EE03A 00000F06 90000335 4000683A 0017883A

Info:   Not here: reserved fields are non-zero

Info: Looking for EPCS registers at address 0x04011300 (with 32bit alignment)

Info:   Initial values: 003FD006 5280040C 501496FA 701CD07A 729CB03A 843FFFC4

Info:   Not here: reserved fields are non-zero

Info: Looking for EPCS registers at address 0x04011400 (with 32bit alignment)

Info:   Initial values: 00000016 00000016 00000260 00000000 00000016 00000001

Info:   Not here: reserved fields are non-zero

Info: Leaving target processor paused

Error: No EPCS registers found: tried looking at addresses    

Error:  0x04011000,

Error:  0x04011100,

Error:  0x04011200,

Error:  0x04011300 and

Error:  0x04011400

Error: Error code: 8 for command: nios2-flash-programmer "D:/Download/DE0_NANO/software/hello_world_0_bsp/flash/hello_world_0_epcs_flash_controller_0.flash" --base=0x4011000 --epcs --sidp=0x4012030 --id=0x0 --timestamp=1517632677 --device=1 --instance=0 '--cable=USB-Blaster on localhost [USB-0]' --program --verbose 

B.5 "No EPCS Registers Found" Error

When you run the flash programmer to program an EPCS device, you get the error:

"No EPCS registers found: tried looking at addresses...."

B.5.1 Probable Cause

The flash programmer can connect with a Nios II JTAG debug module in the FPGA, but it cannot successfully find an EPCS device located at the specified base address.

>> 플래시 프로그래머는 FPGA의 Nios II JTAG 디버그 모듈과 연결할 수 있지만, 지정된 base address에서 EPCS 장치를 발견하는데 성공하지 못했다.

B.5.2 Suggested Actions

• Reconfigure the FPGA with a valid target design via JTAG using the Intel Quartus Prime programmer. If the FPGA is configured by another method, such as by a configuration controller, the pins that connect to the EPCS device might be disabled.

>> 쿼터스 프로그래머를 이용해 JTAG으로 FPGA를 재설정하라. 만약에 FPGA가 configuration controller 와 같은 다른 방법으로 설정된다면 EPCS 장치와 연결되는 핀들이 비활성화 되었을 수 도 있다.

• If you are using quartus_pgm --nios2 from the command line, ensure you specified the correct base address for your EPCS device. You can find the flash memory's base address in Platform Designer.

>> 커맨드 라인에서 quartus_pgm --nios2 을 사용한다면, EPCS 장치에 올바른 base address가 지정되었다 확인하라. Platform Deisigner의 플래시 장치에서 base address를 찾을 수 있다.

• Ensure that the EPCS device is correctly connected to the FPGA on the board. Verify the EPCS connection by running the "Test EPCS" routine in the "Memory Test" software template provided by the Nios II EDS. If the test fails, there is a problem with your memory connection. There are two places to look for the problem:

>> EPCS가 FPGA 보드에 정상적으로 연결되었는지 확인하라. Nios II EDS에 소프트웨어 템플릿으로 제공된 "Memory Test"안의 "Test EPCS"를 실행함으로서 EPCS 연결을 확인하라.

— The physical connection on your target board

— The pin assignments on the top-level FPGA design

• Use the Intel Quartus Prime Programmer to program the EPCS device directly via a JTAG download cable, and verify that the EPCS device successfully configures the FPGA.

• Run quartus_pgm --nios2 from the command line with the --epcs parameter. This command displays information about the flash memory in the EPCS device. For more information, refer to the "Using the Flash Programmer from the Command Line" chapter.

Related Links

Using the Flash Programmer from the Command Line on page 16

Using cable "USB-Blaster [USB-0]", device 1, instance 0x00

Resetting and pausing target processor: OK

Reading System ID at address 0x04012030: verified

Initializing CPU cache (if present)

OK

Downloading 02000000 ( 0%)

Downloading 02010000 (49%)

Downloading 020200A0 (94%)

Downloading 04008000 (99%)

Downloaded 129KB in 1.9s (67.8KB/s)

Verifying 02000000 ( 0%)

Verify failed between address 0x2000000 and 0x200FFFF

Leaving target processor paused

Downloading ELF Process failed 

My problem is resolved now, I just changed the clock source of the EPCS CONTROLLER. The clock was driven from the system clock using a CLOCK BRIDGE.

Now, the clock is driven from a PLL OUTPUT ( the system and the EPCS CONTROLLER clocks are now independent).

Thank you Daixiwen & dsl for helping me. 

DE0_Nano_SOPC DE0_Nano_SOPC_inst(

                      // the_epcs

                       .data0_to_the_epcs(EPCS_DATA0), 

                       .dclk_from_the_epcs(EPCS_DCLK), 

                       .sce_from_the_epcs(EPCS_NCSO), 

                       .sdo_from_the_epcs(EPCS_ASDO), 

                      // the_sdram

                       .zs_addr_from_the_sdram(DRAM_ADDR),

                       .zs_ba_from_the_sdram(DRAM_BA),

                       .zs_cas_n_from_the_sdram(DRAM_CAS_N),

                       .zs_cke_from_the_sdram(DRAM_CKE),

                       .zs_cs_n_from_the_sdram(DRAM_CS_N),

                       .zs_dq_to_and_from_the_sdram(DRAM_DQ),

                       .zs_dqm_from_the_sdram(DRAM_DQM),

                       .zs_ras_n_from_the_sdram(DRAM_RAS_N),

                       .zs_we_n_from_the_sdram(DRAM_WE_N),

                    ); 

module DE0_Nano_SOPC (

output wire [12:0] zs_addr_from_the_sdram,               //                         sdram_wire.addr

output wire [1:0]  zs_ba_from_the_sdram,                 //                                   .ba

output wire        zs_cas_n_from_the_sdram,              //                                   .cas_n

output wire        zs_cke_from_the_sdram,                //                                   .cke

output wire        zs_cs_n_from_the_sdram,               //                                   .cs_n

inout  wire [15:0] zs_dq_to_and_from_the_sdram,          //                                   .dq

output wire [1:0]  zs_dqm_from_the_sdram,                //                                   .dqm

output wire        zs_ras_n_from_the_sdram,              //                                   .ras_n

output wire        zs_we_n_from_the_sdram,               //                                   .we_n

output wire        altpll_sys,                           //                         c0_out_clk.clk

output wire        altpll_sdram,                         //                      altpll_sys_c1.clk

output wire        altpll_io,                            //                         c2_out_clk.clk

output wire        altpll_sys_c3_out,                    //                      altpll_sys_c3.clk

output wire        altpll_adc,                           //                         c4_out_clk.clk

output wire        locked_from_the_altpll_sys,           //          altpll_sys_locked_conduit.export

output wire        phasedone_from_the_altpll_sys,        //       altpll_sys_phasedone_conduit.export

input  wire        in_port_to_the_g_sensor_int,          //   g_sensor_int_external_connection.export

output wire        dclk_from_the_epcs,                   //                      epcs_external.dclk

output wire        sce_from_the_epcs,                    //                                   .sce

output wire        sdo_from_the_epcs,                    //                                   .sdo

input  wire        data0_to_the_epcs,                    //                                   .data0

); 

DE0_Nano_SOPC_sdram sdram (

.clk            (altpll_sys),                                            //   clk.clk

.reset_n        (~rst_controller_002_reset_out_reset),                   // reset.reset_n

.az_addr        (sdram_s1_translator_avalon_anti_slave_0_address),       //    s1.address

.az_be_n        (~sdram_s1_translator_avalon_anti_slave_0_byteenable),   //      .byteenable_n

.az_cs          (sdram_s1_translator_avalon_anti_slave_0_chipselect),    //      .chipselect

.az_data        (sdram_s1_translator_avalon_anti_slave_0_writedata),     //      .writedata

.az_rd_n        (~sdram_s1_translator_avalon_anti_slave_0_read),         //      .read_n

.az_wr_n        (~sdram_s1_translator_avalon_anti_slave_0_write),        //      .write_n

.za_data        (sdram_s1_translator_avalon_anti_slave_0_readdata),      //      .readdata

.za_valid       (sdram_s1_translator_avalon_anti_slave_0_readdatavalid), //      .readdatavalid

.za_waitrequest (sdram_s1_translator_avalon_anti_slave_0_waitrequest),   //      .waitrequest

.zs_addr        (zs_addr_from_the_sdram),                                //  wire.export

.zs_ba          (zs_ba_from_the_sdram),                                  //      .export

.zs_cas_n       (zs_cas_n_from_the_sdram),                               //      .export

.zs_cke         (zs_cke_from_the_sdram),                                 //      .export

.zs_cs_n        (zs_cs_n_from_the_sdram),                                //      .export

.zs_dq          (zs_dq_to_and_from_the_sdram),                           //      .export

.zs_dqm         (zs_dqm_from_the_sdram),                                 //      .export

.zs_ras_n       (zs_ras_n_from_the_sdram),                               //      .export

.zs_we_n        (zs_we_n_from_the_sdram)                                 //      .export

);

DE0_Nano_SOPC_epcs epcs (

.clk           (clk_50),                                                           //               clk.clk

.reset_n       (~rst_controller_001_reset_out_reset),                              //             reset.reset_n

.address       (epcs_epcs_control_port_translator_avalon_anti_slave_0_address),    // epcs_control_port.address

.chipselect    (epcs_epcs_control_port_translator_avalon_anti_slave_0_chipselect), //                  .chipselect

.dataavailable (),                                                                 //                  .dataavailable

.endofpacket   (),                                                                 //                  .endofpacket

.read_n        (~epcs_epcs_control_port_translator_avalon_anti_slave_0_read),      //                  .read_n

.readdata      (epcs_epcs_control_port_translator_avalon_anti_slave_0_readdata),   //                  .readdata

.readyfordata  (),                                                                 //                  .readyfordata

.write_n       (~epcs_epcs_control_port_translator_avalon_anti_slave_0_write),     //                  .write_n

.writedata     (epcs_epcs_control_port_translator_avalon_anti_slave_0_writedata),  //                  .writedata

.irq           (irq_synchronizer_004_receiver_irq),                                //               irq.irq

.dclk          (dclk_from_the_epcs),                                               //          external.export

.sce           (sce_from_the_epcs),                                                //                  .export

.sdo           (sdo_from_the_epcs),                                                //                  .export

.data0         (data0_to_the_epcs)                                                 //                  .export

);

unsaved_epcs_flash_controller_0 epcs_flash_controller_0 (

.clk        (clk_clk),                                                                //               clk.clk

.reset_n    (~rst_controller_reset_out_reset),                                        //             reset.reset_n

.reset_req  (rst_controller_reset_out_reset_req),                                     //                  .reset_req

.address    (mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_address),    // epcs_control_port.address

.chipselect (mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_chipselect), //                  .chipselect

.read_n     (~mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_read),      //                  .read_n

.readdata   (mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_readdata),   //                  .readdata

.write_n    (~mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_write),     //                  .write_n

.writedata  (mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_writedata),  //                  .writedata

.irq        (irq_mapper_receiver1_irq),                                               //               irq.irq

.dclk       (),                                                                       //          external.export

.sce        (),                                                                       //                  .export

.sdo        (),                                                                       //                  .export

.data0      ()                                                                        //                  .export

);

module unsaved (

input  wire       clk_clk,                          //                       clk.clk

output wire [7:0] pio_0_external_connection_export, // pio_0_external_connection.export

input  wire       reset_reset_n                     //                     reset.reset_n

); 

module unsaved (

input  wire        clk_clk,                          //                       clk.clk

output wire        epcs_dclk,                        //                      epcs.dclk

output wire        epcs_sce,                         //                          .sce

output wire        epcs_sdo,                         //                          .sdo

input  wire        epcs_data0,                       //                          .data0

output wire [7:0]  pio_0_external_connection_export, // pio_0_external_connection.export

input  wire        reset_reset_n,                    //                     reset.reset_n

output wire [12:0] sdram_addr,                       //                     sdram.addr

output wire [1:0]  sdram_ba,                         //                          .ba

output wire        sdram_cas_n,                      //                          .cas_n

output wire        sdram_cke,                        //                          .cke

output wire        sdram_cs_n,                       //                          .cs_n

inout  wire [31:0] sdram_dq,                         //                          .dq

output wire [3:0]  sdram_dqm,                        //                          .dqm

output wire        sdram_ras_n,                      //                          .ras_n

output wire        sdram_we_n                        //                          .we_n

);

Error (13076): The node has multiple drivers due to the always-enabled I/O buffer 

Operating Conditions

When Cyclone IV devices are implemented in a system, they are rated according to a set of defined parameters. To maintain the highest possible performance and reliability of Cyclone IV devices, you must consider the operating requirements described in this chapter. Cyclone IV devices are offered in commercial, industrial, extended industrial and, automotive grades. Cyclone IV E devices offer –6 (fastest), –7, –8, –8L, and –9L speed grades for commercial devices, –8L speed grades for industrial devices, and –7 speed grade for extended industrial and automotive devices. Cyclone IV GX devices offer –6 (fastest), –7, and –8 speed grades for commercial devices and –7 speed grade for industrial devices. 

자일링스의 이지패스 솔루션은 FPGA에서 디자인한 반도체를 주문형반도체(ASIC)로 만드는 대신, 저가의 프로그래머블 반도체를 통해 양산해주는 것이다. 이를 통해 시스템업체 및 반도체 업체들은 반도체 소량 양산할 경우 ASIC 과정을 거칠 필요가 없어 시스템 설계 시간을 줄이고 테스트 비용을 줄일 수 있다. 

대부분의 비용 절감 요소가 디자인 옵션을 제한하고 최적화되지 않은 부품이나 패키지를 고객에게 과도하게 강요한다. 반면, 이지패스-6 FPGA는 기본 제품군의 모든 디바이스, 패키지, 모든 속도 및 온도 등급을 지원하는 유일한 FPGA 절감 솔루션이라는 점에서 유례 없는 제품이다. 이는 고객이 디자인을 구현하고 비용을 절감 하기 위해 모든 버텍스®-6 LX, LXT, SXT 및 HXT 디바이스를 선택할 수 있게 되었음을 의미하는 것이다.

기타 다른 방식과는 달리, 이지패스-6 FPGA는 ASIC 컨버전이나 라우팅 강화(routing-hardened) FPGA가 아니다. 버텍스-6에서 이지패스-6 디바이스로 마이그레이션 할 때 추가적인 디자인 제약이 따르지 않는다. 또한 FPGA 디자인을 재 작업하거나 다시 최적화할 필요도 없으며, 회로보드를 다시 레이아웃 할 필요도 없다. 고객이 자일링스에 디자인파일을 제공하면, 실리콘 웨이퍼를 표준 FPGA와 동일한 전기적 파라미터로 테스트하여 고객 디자인에 사용되는 특정 리소스에 대해 저장한다. 그 후 6주 내에 파생 다이가 조립 및 표시되고 최종 테스트를 거쳐 그 기능과 성능을 확인한다. 자일링스에서 최초로 단 기간 내에 프로토타입에서 즉시 양산이 가능한 디바이스를 제공하는 FPGA 비용 절감 솔루션을 선보이게 된 것이다.

Info: 2018. 2. 1 오전 11:40:05 - (정보) elf2flash: args = --input=D:/Download/DE0_NANO/software/hello_world_0/hello_world_0.elf --output=D:/Download/DE0_NANO/software/hello_world_0_bsp/flash/hello_world_0_epcs_flash_controller_0.flash --epcs --verbose

Info: 2018. 2. 1 오전 11:40:05 - (미세) elf2flash: Starting

Info: 2018. 2. 1 오전 11:40:05 - (보다 미세) elf2flash: Program Record: 3964 bytes destined for 0x8000

Info: 2018. 2. 1 오전 11:40:05 - (보다 미세) elf2flash: Program Record: 724 bytes destined for 0x9250

Info: 2018. 2. 1 오전 11:40:05 - (보다 미세) elf2flash: Start Record: 8020

Info: 2018. 2. 1 오전 11:40:05 - (미세) elf2flash: Done

Info: Using cable "USB-Blaster [USB-0]", device 1, instance 0x00

Info: Resetting and pausing target processor: 

Info: OK

Info: Reading System ID at address 0x00012030: 

Info: verified

Info: Processor data bus width is 32 bits

Info: Looking for EPCS registers at address 0x00011000 (with 32bit alignment)

Info:   Initial values: 0001703A 04C00074 9801483A 9CFFF804 983FFD1E 0000203A

Info:   Not here: reserved fields are non-zero

Info: Looking for EPCS registers at address 0x00011100 (with 32bit alignment)

Info:   Initial values: 93000237 6300080C 603FFD26 90000335 A8000C26 03010004

Info:   Not here: reserved fields are non-zero

Info: Looking for EPCS registers at address 0x00011200 (with 32bit alignment)

Info:   Initial values: 02C02004 002EE03A 00000F06 90000335 4000683A 0017883A

Info:   Not here: reserved fields are non-zero

Info: Looking for EPCS registers at address 0x00011300 (with 32bit alignment)

Info:   Initial values: 003FD006 5280040C 501496FA 701CD07A 729CB03A 843FFFC4

Info:   Not here: reserved fields are non-zero

Info: Looking for EPCS registers at address 0x00011400 (with 32bit alignment)

Info:   Initial values: 00000000 00000000 00000260 00000000 00000000 00000001

Info:   Valid registers found

Info: EPCS signature is 0x00

Info: EPCS identifier is 0x000000

Info: Leaving target processor paused

Error: No EPCS layout data - looking for section [EPCS-000000]

Error: Unable to use EPCS device

Error: Error code: 8 for command: nios2-flash-programmer "D:/Download/DE0_NANO/software/hello_world_0_bsp/flash/hello_world_0_epcs_flash_controller_0.flash" --base=0x11000 --epcs --sidp=0x12030 --id=0x0 --timestamp=1517370555 --device=1 --instance=0 '--cable=USB-Blaster on localhost [USB-0]' --program --verbose  

10. Click SOF Data, and select Add File, and select your .sof file

11. Click Add Hex data, select Relative addressing, and select your .hex file created above

12. Now push generate. You should verify that the generated .map file has Page_0 at a start address of 0x0, and the hex file at a start address 1 after the end address of Page_0

13. Now in the Quartus II Programmer, select Add File and select your .jic file. Check the Program box next to the .jic file, and push Start

Creating the .jic file:

In Quartus, open the Convert "Programming File..." utility

Set the "Programming file type:" to "JTAG Indirect Configuration File (.jic)"

In "Input files to convert" select "Flash Loader", click "Add Device..." and choose your target FPGA device

If you are configuring the FPGA from the serial flash:

In "Input files to convert" select "SOF Data", click "Add File..." and select your FPGA .sof file

-With "SOF Data" selected, click "Properties", in the "SOF Data Properies dialogue box:

-Set "Address mode for selected pages to" to "Start"

Set "Start address (32-bit hexidecimal:) to 0x0.

In "Input files to convert" click "Add Hex Data", in the "Add Hex Data" dialogue box:

Set "Addressing mode" to "Absolute addressing"

Select your hex file using the "..." button next to the "Hex file" field

Click "OK"

Check "Create Memory Map File". This is useful for debugging.

Generate the .jic file and program it into the serial flash with the Quartus Programmer 

13:50:21 **** Build of configuration Nios II for project hello_world_0 ****

make mem_init_generate 

Info: Building ../hello_world_0_bsp/

C:/intelFPGA_lite/17.1/nios2eds/bin/gnu/H-x86_64-mingw32/bin/make --no-print-directory -C ../hello_world_0_bsp/

[BSP build complete]

Post-processing to create mem_init/hdl_sim/unsaved_epcs_flash_controller_0_boot_rom.hex...

elf2hex hello_world_0.elf 0x00011000 0x000117ff --width=32 --little-endian-mem --create-lanes=0 --no-zero-fill mem_init/hdl_sim/unsaved_epcs_flash_controller_0_boot_rom.hex

Post-processing to create mem_init/unsaved_onchip_memory2_0.hex...

elf2hex hello_world_0.elf 0x00008000 0x0000ffff --width=32 --little-endian-mem --create-lanes=0 mem_init/unsaved_onchip_memory2_0.hex

Post-processing to create mem_init/hdl_sim/unsaved_epcs_flash_controller_0_boot_rom.dat...

elf2dat --infile=hello_world_0.elf --outfile=mem_init/hdl_sim/unsaved_epcs_flash_controller_0_boot_rom.dat \

--base=0x00011000 --end=0x000117ff --width=32 \

--little-endian-mem --create-lanes=0 

Post-processing to create mem_init/hdl_sim/unsaved_onchip_memory2_0.dat...

elf2dat --infile=hello_world_0.elf --outfile=mem_init/hdl_sim/unsaved_onchip_memory2_0.dat \

--base=0x00008000 --end=0x0000ffff --width=32 \

--little-endian-mem --create-lanes=0 

Post-processing to create mem_init/hdl_sim/unsaved_epcs_flash_controller_0_boot_rom.sym...

nios2-elf-nm -n hello_world_0.elf > mem_init/hdl_sim/unsaved_epcs_flash_controller_0_boot_rom.sym

Post-processing to create mem_init/hdl_sim/unsaved_onchip_memory2_0.sym...

nios2-elf-nm -n hello_world_0.elf > mem_init/hdl_sim/unsaved_onchip_memory2_0.sym

Post-processing to create unsaved_epcs_flash_controller_0_boot_rom.flash...

elf2flash --input=hello_world_0.elf --outfile=unsaved_epcs_flash_controller_0_boot_rom.flash --sim_optimize=0 --little-endian-mem \

 --epcs 

Post-processing to create mem_init/meminit.spd...

Post-processing to create mem_init/meminit.qip...

13:50:26 Build Finished (took 4s.961ms) 

3.3.1.3 EPCS Parameters

3.3.2 Programming Both Hardware and Software into an EPCS/EPCQ

Device

The --base parameter is not available for EPCS/EPCQ devices, because in EPCS/EPCQ devices, FPGA configuration data must start at address 0x0. However, if you are programming both an FPGA configuration and a Nios II software executable in the EPCS/EPCQ device, the --after parameter lets you position the software executable directly after the FPGA configuration data.

Convert the FPGA configuration file first using sof2flash. When converting the Nios II software executable, use the --after parameter, and specify the FPGA configuration S-record file. The S-record output for the software executable starts at the first address unused by the FPGA configuration. Refer to the second example under the “elf2flash Command-Line Examples” chapter.

Note: elf2flash does not insert the FPGA configuration into the output file. It simply leaves space, starting at offset 0x0, that is large enough for the configuration data.

Note: In Intel Quartus Prime software version 13.1 and onwards, the -epcs/--epcq option in sof2flash generates .flash file with a SOF header, which contains the SOF length.

This change is required for V-series devices and above for new SOF format, and to allow for future SOF format variations. The Nios II bootcopier loads the Nios II software executable from EPCS/EPCQ devices based on the SOF length. For more information about how to program EPCS/EPCQ devices, refer to the "KDB Solution rd11192013_118" webpage.

Related Links

• elf2flash Command-Line Examples on page 25

• KDB Solution rd11192013_118 

13:01:21 **** Incremental Build of configuration Nios II for project hello_world_0_bsp ****

make all 

Makefile not up to date.

../../unsaved.sopcinfo has been modified since the BSP was generated.

Generate the BSP to update the Makefile, and then build again.

To generate from Eclipse:

 1. Right-click the BSP project.

 2. In the Nios II Menu, click Generate BSP.

To generate from the command line:

 nios2-bsp-generate-files --settings=<settings file> --bsp-dir=<target bsp files directory>

make: *** [public.mk] Error 1

13:01:22 Build Finished (took 946ms)

EPCS Controller-Based Boot Copier

EPCS controller-based boot copier supports EPCS memory only. Boot copier is stored in the ROM within

the EPCS flash controller. The boot copier is included during Qsys and Quartus Prime project compila‐

tion time.

The next stage boot image is located in the EPCS memory flash. The EPCS controller-based boot copier is

automatically appended into the SREC image (*.flash) file during the elf2flash utility execution in the

Nios II Flash Programming flow method.