spi 통신 예제(linux)

쓸일이 곧 생길게야.... (동공지진)

 

[링크 : https://github.com/torvalds/linux/blob/master/tools/spi/spidev_test.c]

+ 2021.02.08

 

It's easy to be confused here, and the vendor documentation you'll
find isn't necessarily helpful.  The four modes combine two mode bits:

 - CPOL indicates the initial clock polarity.  CPOL=0 means the
   clock starts low, so the first (leading) edge is rising, and
   the second (trailing) edge is falling.  CPOL=1 means the clock
   starts high, so the first (leading) edge is falling.

 - CPHA indicates the clock phase used to sample data; CPHA=0 says
   sample on the leading edge, CPHA=1 means the trailing edge.

   Since the signal needs to stablize before it's sampled, CPHA=0
   implies that its data is written half a clock before the first
   clock edge.  The chipselect may have made it become available.

[링크 : https://www.kernel.org/doc/Documentation/spi/spi-summary]