'이론 관련/컴퓨터 관련'에 해당되는 글 36건

  1. 2018.06.22 MNIST 데이터베이스
  2. 2018.06.11 VGA DMT 스펙
  3. 2018.06.08 vga 타이밍
  4. 2018.06.01 vga porch (4)
  5. 2018.05.30 VGA(RGB) 파형 측정
  6. 2018.05.30 VGA Pattern Generator 관련 검색
  7. 2018.05.29 hdmi pinout
  8. 2018.05.29 VGA 관련 자료 검색중
  9. 2018.04.24 I2c smbus slave interrupt
  10. 2018.03.19 haze / defog

수정된 NIST 데이터베이스

기계학습에서 사용되는 숫자 손글씨 6만개 + 테스트용 1만개 셋


Modified National Institute of Standards and Technology database

[링크 : https://ko.wikipedia.org/wiki/MNIST_데이터베이스]

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해상도에 따라 Sync의 polarity가 다르네..

규칙성을 찾고 싶은데 딱히 그런건 없고

VESA 표준에 의해서 해상도 별로 지정된 값이 다 다르다


Timing Name = 640 x 480 @ 60Hz;

Hor Pixels = 640; // Pixels

Ver Pixels = 480; // Lines

Hor Frequency = 31.469; // kHz = 31.8 usec / line

Ver Frequency = 59.940; // Hz = 16.7 msec / frame

Pixel Clock = 25.175; // MHz = 39.7 nsec ± 0.5%

Character Width = 8; // Pixels = 317.8 nsec

Scan Type = NONINTERLACED; // H Phase = 2.0 %

Hor Sync Polarity = NEGATIVE; // HBlank = 18.0% of HTotal

Ver Sync Polarity = NEGATIVE; // VBlank = 5.5% of VTotal

Hor Total Time = 31.778; // (usec) = 100 chars = 800 Pixels

Hor Addr Time = 25.422; // (usec) = 80 chars = 640 Pixels

Hor Blank Start = 25.740; // (usec) = 81 chars = 648 Pixels

Hor Blank Time = 5.720; // (usec) = 18 chars = 144 Pixels

Hor Sync Start = 26.058; // (usec) = 82 chars = 656 Pixels

// H Right Border = 0.318; // (usec) = 1 chars = 8 Pixels

// H Front Porch = 0.318; // (usec) = 1 chars = 8 Pixels

Hor Sync Time = 3.813; // (usec) = 12 chars = 96 Pixels

// H Back Porch = 1.589; // (usec) = 5 chars = 40 Pixels

// H Left Border = 0.318; // (usec) = 1 chars = 8 Pixels

Ver Total Time = 16.683; // (msec) = 525 lines HT – (1.06xHA)

Ver Addr Time = 15.253; // (msec) = 480 lines = 4.83

Ver Blank Start = 15.507; // (msec) = 488 lines

Ver Blank Time = 0.922; // (msec) = 29 lines

Ver Sync Start = 15.571; // (msec) = 490 lines

// V Bottom Border = 0.254; // (msec) = 8 lines

// V Front Porch = 0.064; // (msec) = 2 lines

Ver Sync Time = 0.064; // (msec) = 2 lines

// V Back Porch = 0.794; // (msec) = 25 lines

// V Top Border = 0.254; // (msec) = 8 lines

 Timing Name = 1280 x 960 @ 60Hz;

Hor Pixels = 1280; // Pixels

Ver Pixels = 960; // Lines

Hor Frequency = 60.000; // kHz = 16.7 usec / line

Ver Frequency = 60.000; // Hz = 16.7 msec / frame

Pixel Clock = 108.000; // MHz = 9.3 nsec ± 0.5%

Character Width = 8; // Pixels = 74.1 nsec

Scan Type = NONINTERLACED; // H Phase = 6.0 %

Hor Sync Polarity = POSITIVE; // HBlank = 28.9% of HTotal

Ver Sync Polarity = POSITIVE; // VBlank = 4.0% of VTotal

Hor Total Time = 16.667; // (usec) = 225 chars = 1800 Pixels

Hor Addr Time = 11.852; // (usec) = 160 chars = 1280 Pixels

Hor Blank Start = 11.852; // (usec) = 160 chars = 1280 Pixels

Hor Blank Time = 4.815; // (usec) = 65 chars = 520 Pixels

Hor Sync Start = 12.741; // (usec) = 172 chars = 1376 Pixels

// H Right Border = 0.000; // (usec) = 0 chars = 0 Pixels

// H Front Porch = 0.889; // (usec) = 12 chars = 96 Pixels

Hor Sync Time = 1.037; // (usec) = 14 chars = 112 Pixels

// H Back Porch = 2.889; // (usec) = 39 chars = 312 Pixels

// H Left Border = 0.000; // (usec) = 0 chars = 0 Pixels

Ver Total Time = 16.667; // (msec) = 1000 lines HT – (1.06xHA)

Ver Addr Time = 16.000; // (msec) = 960 lines = 4.1

Ver Blank Start = 16.000; // (msec) = 960 lines

Ver Blank Time = 0.667; // (msec) = 40 lines

Ver Sync Start = 16.017; // (msec) = 961 lines

// V Bottom Border = 0.000; // (msec) = 0 lines

// V Front Porch = 0.017; // (msec) = 1 lines

Ver Sync Time = 0.050; // (msec) = 3 lines

// V Back Porch = 0.600; // (msec) = 36 lines

// V Top Border = 0.000; // (msec) = 0 lines


640x480@60 기준

Front Porch 8 pixel

Sync 96 pixel

Back Porch 40 pixel

Left Border 8 pixel

Addr Time 640 pixel

Right Border 8 pixel

실 데이터 영역 640 + 좌우 여백(8 pixel * 2) + porch (8+40) + sync (96) = 800pixel




DMTv1r11.pdf

[링크 : http://caxapa.ru/thumbs/361638/DMTv1r11.pdf]

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The different modes that Advanced Timing allows end users to select are:

  • Electronic Industries Alliance (EIA-861B) refers to a CEA/EIA standard which consists of display timing and formats supported by Digital Televisions
  • Generalized Timing Formula (GTF) is a method of generating industry standard timings used by a wide variety of display products
  • Display Monitor Timings (DMT) are a list of VESA standard pre-defined timings which are commonly used within the Computer industry.
  • Coordinated Video Timings (CVT) were released on March 2003 as the newest VESA standard for generating display timings
  • Coordinated Video Timings-Reduced Blanking (CVT-RB) is geared specifically for non-CRT display devices. CVT-RB offers reduced horizontal and vertical blanking periods and allows a lower pixel clock rate and higher frame rates.
  • EDID Timing is the preferred timing standard defined by the display's Extended Display Identification Data (EDID) value. EDID is a standard data structure that defines the display device's configuration data and mode support which allows optimum use of the display 

[링크 : http://www.nvidia.com/object/advanced_timings.html]

    [링크 : https://forums.geforce.com/default/topic/379915/timing-standard-what-is-it-/]


The standard was adopted in 2002 and superseded the Generalized Timing Formula. 

[링크 : https://en.wikipedia.org/wiki/Coordinated_Video_Timings]


+

2018.06.11

제목대로 DMT 타이밍에 대한 VESA 문서

[링크 : http://caxapa.ru/thumbs/361638/DMTv1r11.pdf]


+

 타이밍 모드

 표준

 CEA/EIA-861B

 ???

 GTF 

 1999

 DMT

 2007 (Version 1.0 Rev 0.11)

 CVT 

 2002 (Version 1.0 Rev 0.9)

 CVT-RB

 2007 (Version 1.0 Rev 0.11)

 EDID 

 1996 (Version 1.0 Rev 0.4)


he standard was adopted in 1999, and was superseded by the Coordinated Video Timings specification in 2002. 

[링크 : https://en.wikipedia.org/wiki/Generalized_Timing_Formula]


+

라즈베리 파이에서 HDMI 모드 중에 CEA / DMT가 있던게 생각남..

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vga 관련 문서를 찾다 보니 구현했는데 안되요~ 라는 말이 있어서 스펙을 좀더 찾아 보는중.

아래는 front porch - sync - back porch - data 순서인데

중간에 문장을 보면.. data 에서만 HSync가 High로 나오고 나머지는 Low로 해주면 될 듯


ParameterValueUnit
Pixel clock frequency25.175MHz[10]
Horizontal frequency31.469kHz
Horizontal pixels640
Horizontal sync polarityNegative
Total time for each line31.778µs
Front porch (A)0.636µs
Sync pulse length (B)3.813µs
Back porch (C)1.907µs
Active video (D)25.422µs

(Total horizontal sync and blanking time = 6.356 µs; equivalent to pixel widths of A = 16, B = 96, C = 48, D = 640 and each complete line = 800)

[링크 : https://en.wikipedia.org/wiki/Video_Graphics_Array]


기존의 아날로그 영상의 경우에는 sync - back porch - data - front porch 순서로 되어있다.

편의상 front - sync - back - data 순서로 하다보니 처음에 sync가 아닌 front가 와서 인식 못하는건 아닐까?

[링크 : https://en.wikipedia.org/wiki/Analog_television#Structure_of_a_video_signal]


+

[링크 : http://www.mcamafia.de/pdf/ibm_vgaxga_trm2.pdf] VGA 표준?


VSync는 가장 첫줄 할때만

[링크 : http://www.ccm.ece.vt.edu:8444/twiki/pub/Main/LectureNotes/23-VGA.pdf]

[링크 : http://www.eng.utah.edu/~cs3710/labs/VGA.pdf]


타이밍 정보

Sync만 보고, porch는 Data에 붙여 버렸네?

[링크 : http://www.epanorama.net/documents/pc/vga_timing.html]


"VGA industry standard" 640x480 pixel mode

Clock frequency 25.175 MHz

Line  frequency 31469 Hz

Field frequency 59.94 Hz


One line

  8 pixels front porch

96 pixels horizontal sync

 40 pixels back porch

  8 pixels left border

640 pixels video

  8 pixels right border

---

800 pixels total per line


One field

  2 lines front porch

  2 lines vertical sync

 25 lines back porch

  8 lines top border

480 lines video

  8 lines bottom border

---

525 lines total per field               


[링크 : https://courses.cs.washington.edu/courses/cse467/00wi/lectures/ppt/VGAinterface.ppt]



+


[링크 : https://timetoexplore.net/blog/arty-fpga-vga-verilog-01]

[링크 : https://github.com/pmezydlo/DE0-Nano-SOC-VGA]


50MHz = 0.02us

[링크 : https://www.unitjuggler.com/convert-frequency-from-MHz-to-%C2%B5s(p).html?val=50]

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  1. 성탁

    http://ele-tech.net/vga-doc1/

    여기 링크 중간쯤에 VSYNC, HSYNC 파형보면 될듯....

    Porch구간에도 High로 나가는거구 형이 쓴내용은 보니깐 DE signal 말하는거임...

    2018.06.04 10:42 신고 [ ADDR : EDIT/ DEL : REPLY ]
  2. 성탁

    DE가 data enable....

    porch 말고 실제 pixel data입력되는 부분~!!

    2018.06.04 12:46 신고 [ ADDR : EDIT/ DEL : REPLY ]
    • 아마 그건... DAC 쓰면서 컬러출력하는 부분이려나? 나야 그거 없이 일단 sync만 발생시키고 비디오는 안쓰다 보니
      굳이 DE가 있을 이유가.. ㅠㅠ

      2018.06.04 13:13 신고 [ ADDR : EDIT/ DEL ]

1920*1080*60Hz 파형

일단.. 알아낸건

RGB 쪽은 1.2V 정도이고

H/V는 5V 정도?


R

영상의 시작과 끝이 잡히긴 하는데..

H/V 동기와 같이 볼 수 있는게 아니라(손으로 찍다 보니.. 두 채널 짜리긴 해도 못 함 ㅠㅠ) 아쉬움..

0.7ms 정도의 0V는 HBI(Horizontal Blanking Interval) 같은데

그 앞에 약한놈은 멀까... 배경이 푸루딩딩해서 빨간 성분이 하나도 없는 부분인가?

SAMSUNG | SHV-E250S | Aperture priority | Center-weighted average | 1/15sec | F/2.6 | 0.00 EV | 3.7mm | ISO-200 | Flash did not fire | 2018:05:30 14:14:31


13번 핀. H가 맞는거 같은데 왜 이렇게 낮게 나오지? 잘못 찍었나?

SAMSUNG | SHV-E250S | Aperture priority | Center-weighted average | 1/15sec | F/2.6 | 0.00 EV | 3.7mm | ISO-250 | Flash did not fire | 2018:05:30 14:15:48


V

67,490Hz / 60 = 1,124

오차범위 고려하면 1080 + 45 VBI?

SAMSUNG | SHV-E250S | Aperture priority | Center-weighted average | 1/15sec | F/2.6 | 0.00 EV | 3.7mm | ISO-250 | Flash did not fire | 2018:05:30 14:19:07



+

2018.05.31

이게 Vsync 이고, 위에  67.49 나온게 Hsync 일듯?

SAMSUNG | SHV-E250S | Aperture priority | Center-weighted average | 1/15sec | F/2.6 | 0.00 EV | 3.7mm | ISO-250 | Flash did not fire | 2018:05:30 14:17:28




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픽셀 클럭 등등등.. 막 쑤셔 넣음..


front-back porch

[링크 : http://web.mit.edu/6.111/www/s2004/NEWKIT/vga.shtml]

[링크 : https://nathandumont.com/blog/vga-primer]

[링크 : https://eewiki.net/pages/viewpage.action?pageId=15925278]


[링크 : http://www.eng.ucy.ac.cy/theocharides/Courses/ECE664/VGA.pdf]

[링크 : https://timetoexplore.net/blog/video-timings-vga-720p-1080p] + EDID

[링크 : http://martin.hinner.info/vga/timing.html]

[링크 : http://tinyvga.com/vga-timing]

[링크 : http://www.ni.com/white-paper/4750/ko/]

[링크 : http://monitorinsider.com/cable_bandwidth.html]

[링크 : https://www.monitortests.com/pixelclock.php] << 계산기.. 쓰는법 모르겠음


[링크 : http://forum.falinux.com/zbxe/?document_srl=562729&mid=lecture_tip&page=3]


[링크 : https://en.wikipedia.org/wiki/Broadcast_television_systems]

[링크 : https://en.wikipedia.org/wiki/Horizontal_blanking_interval]

[링크 : https://en.wikipedia.org/wiki/Vertical_blanking_interval]


+

H/Vsync는 5V이긴 한데 3.3V 상관없나?

[링크 : http://www.javiervalcarce.eu/html/vga-signal-format-timming-specs-en.html]

[링크 : https://electronics.stackexchange.com/.../programming-pattern-to-generate-vga-signal-with-micro-controller]


+

ATmega88로 만들기 ㄷㄷ

[링크 : https://www-user.tu-chemnitz.de/~heha/Mikrocontroller/VgaGen/VgaGen.en.htm]

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HDMI 핀 배열 및 신호 관련 정보 검색


[링크 : http://pinouts.ru/visual/gen/hdmi.jpg]

[링크 : http://pinouts.ru/Video/hdmi_pinout.shtml]


TMDS는 0/1/2+CLK로 구성되고

CEC와 DDC 그리고 Hotplug 및 5V 전원이 공급된다.

Pins 1 through 9 carry the three TMDS data channels (Transition Minimized Differential Signaling – the technology that allows DVI and HDMI to send high-speed digital data), three pins per channel. TMDS data includes both video and audio information, and each channel has three separate lines for + values, - values, and a ground or data shield.


Pins 10 through 12 carry data for the TMDS clock channel, which helps keep the signals in synchronization. As with the TMDS data channels, there are separate lines for + values, - values, and a data shield.


Pin 13 is carries the CEC (Consumer Electronics Control) channel, used for sending command and control data between connected devices.


Pin 14 is reserved for future use.


Pins 15 and 16 are dedicated to the DDC (Display Data Channel), used for communicating EDID (Extended Display Identification Channel) information between devices.


Pin 17 is a data shield for the CEC and DDC channels.


Pin 18 carries a low-voltage (+5V) power supply.


Pin 19 is the Hot Plug Detect, dedicated to monitoring power up/down and plug/unplug events. 

[링크 : https://www.hdmi.org/installers/insidehdmicable.aspx]


데이터는 8b/10b로 인코딩 됨

Both HDMI and DVI use TMDS to send 10-bit characters that are encoded using 8b/10b encoding

[링크 : https://en.wikipedia.org/wiki/HDMI]


2.8V~3.3V로 표현.. TMDS니까 디퍼런셜 라인의 경우 어떻게 표현되려나?

디지털이니까 0과 1만 뒤집어 주면 되려나?

Basics

 HDMI leverages on the successful transition minimized differential signaling (TMDS) technology. The differential signals are +3.3 Volts, terminated in 50 Ω with nominal amplitude transitions of 500 mV (+2.8 V to +3.3 V). The voltage swing can vary from 150 mV to 800 mV. The signals have rise times of the order of 100 ps 

[링크 : http://download.tek.com/document/61W_17974_6_HR_Letter_0.pdf]


6.2.2 Video Control Signals : HSYNC, VSYNC

During the Data Island period, HDMI carries HSYNC and VSYNC signals using encoded bits on Channel 0. During Video Data periods, HDMI does not carry HSYNC and VSYNC and the Sink should assume that these signals remain constant. During Control periods, HDMI carries HSYNC and VSYNC signals through the use of four different control characters on TMDS Channel 0. 

[링크 : http://d1.amobbs.com/bbs_upload782111/files_51/ourdev_716302E34B9Q.pdf]


BGR 순서로 채널이 배정되는게 맞는 듯?

[링크 : http://www.wireworldcable.co.uk/hdmi_tech.html]


[링크 : https://www.cablestogo.com/learning/library/digital-signage/intro-to-tmds]

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640*480에 대한 VHDL 코드 인듯?

0.1 + 0.2 + 0.4V 합치면 0.7V 니까.. 3비트 씩 해서 8(2^3)  * 8 * 8 = 512 컬러 인가?

A VGA video signal contains 5 active signals:

• horizontal sync: digital signal, used for synchronisation of the video

• vertical sync: digital signal, used for synchronisation of the video

• red (R): analog signal (0-0.7 v), used to control the color

• green (G): analog signal (0-0.7 v), used to control the color

• blue (B): analog signal (0-0.7 v), used to control the color 

흐음.. 이건 어떻게 해석을 해야 하나?


[링크 : http://lslwww.epfl.ch/pages/teaching/cours_lsl/ca_es/VGA.pdf]



요즘 사용하는건 I2C 들어간 DDC2 방식이라고 해야하나?

[링크 : https://en.wikipedia.org/wiki/Display_Data_Channel]

[링크 : http://pinouts.ru/Video/VGA15_pinout.shtml]

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I2C slave에서 마스터로 전송할 데이터가 생길 경우에는

폴링을 기다리거나, 마스터로 연결된 interrupt 핀이 있어야 한다.


Case 1: Slave has an interrupt pin


You need to connect this interrupt pin to master microcontroller. Every time the slave has some data, it should raise an interrupt. At that point, master will read the available data.


Case 2: Slave doesn't have an interrupt pin


Polling is the only option in this case. Master keeps reading all the slaves at regular interval and keeps comparing the received data with old one. If the data has changed, master will take appropriate action. You need to decide the interval according to your application. 

[링크 : https://electronics.stackexchange.com/questions/307630/slave-wants-to-send-data-to-master-in-i2c/307641]



다만 SMBUS에서는

slave가 mater 처럼 작동하여 호스트(0x08)에게 자신의 주소와 2바이트 정보는 던질 수 있도록 되어있다.

아니면 SMBALERT# 시그널을 통해 주의를 요청인데 이게 인터럽트 라인인 듯?

Arbitration in SMBus

Although conceptually a single-master bus, a slave device that supports the "host notify protocol" acts as a master to perform the notification. It seizes the bus and writes a 3-byte message to the reserved "SMBus Host" address (0x08), passing its address and two bytes of data. When two slaves try to notify the host at the same time, one of them will lose arbitration and need to retry.

An alternative slave notification system uses the separate SMBALERT# signal to request attention. In this case, the host performs a 1-byte read from the reserved "SMBus Alert Response Address" (0x0c), which is a kind of broadcast address. All alerting slaves respond with a data bytes containing their own address. When the slave successfully transmits its own address (winning arbitration against others) it stops raising that interrupt. In both this and the preceding case, arbitration ensures that one slave's message will be received, and the others will know they must retry.

SMBus also supports an "address resolution protocol", wherein devices return a 16-byte "universal device ID" (UDID). Multiple devices may respond; the one with the least UDID will win arbitration and be recognized. 

[링크 : http://www.microchip.com/forums/m/tm.aspx?m=795577&p=1]

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