vga 640x480 실패중 그리고 800x600x60

소스 코드 수정중인데 안나오네

vga640x480 vga( CLOCK_50, KEY[0], LED, GP0[6], GP0[5], {GP0[16],GP0[19],GP0[18],GP0[21]}, {GP0[12],GP0[15],GP0[14],GP0[17]}, {GP0[8],GP0[9],GP0[10],GP0[13]} );

module vga640x480( input clk, input rst, output [7:0] LED, output hsync, output vsync, output [3:0] r, output [3:0] g, output [3:0] b ); parameter HSYNC = 189; parameter HBP = (HSYNC + 95); parameter HVID = (HBP + 1260); parameter HFP = (HVID + 47); parameter VSYNC = 3000; parameter VBP = (VSYNC + 51000); parameter VVID = (VBP + 762500); parameter VFP = (VVID + 17500); reg [19:0] cnt; always @ (posedge clk or negedge rst) begin if (!rst) begin cnt <= 0; end else begin cnt <= cnt + 1; if(cnt > 834000) cnt <= 0; end end assign hsync = ((cnt % 1590) < 189) ? 0 : 1; assign vsync = (cnt < 3000) ? 0 : 1; assign r = ((hsync & vsync) == 1 ? 4'b1111 : 4'b0000); assign g = ((hsync & vsync) == 1 ? 4'b1111 : 4'b0000); assign b = ((hsync & vsync) == 1 ? 4'b1111 : 4'b0000); assign LED[0] = ~vsync; assign LED[1] = ~hsync; endmodule

V sync는 59.95

H sync는 31.31kHz 이고

sync 길이도 파형도 맞는거 같은데..

Vsync 60us 근처

Hsync 4us 근처

왜 안될까...

+

module vga800x600x60( input clk, input rst, output [7:0] LED, output hsync, output vsync, output [3:0] r, output [3:0] g, output [3:0] b ); parameter HSYNC = 160; parameter HBP = (HSYNC + 95); parameter HVID = (HBP + 1260); parameter HFP = (HVID + 47); parameter VSYNC = 5300; parameter VBP = (VSYNC + 51000); parameter VVID = (VBP + 762500); parameter VFP = (VVID + 17500); reg [19:0] cnt; always @ (posedge clk or negedge rst) begin if (!rst) begin cnt <= 0; end else begin cnt <= cnt + 1; if(cnt > 828950) cnt <= 0; end end assign hsync = ((cnt % 1320) < 160) ? 0 : 1; assign vsync = (cnt < 5300) ? 0 : 1; assign r = ((hsync & vsync) == 1 ? 4'b1111 : 4'b0000); assign g = ((hsync & vsync) == 1 ? 4'b1111 : 4'b0000); assign b = ((hsync & vsync) == 1 ? 4'b1111 : 4'b0000); assign LED[0] = ~vsync; assign LED[1] = ~hsync; endmodule

For VESA 800*600 @ 60Hz:  Fh (kHz) :37.88  A (us) :26.4  B (us) :3.2  C (us) :2.2  D (us) :20.0  E (us) :1.0  Fv (Hz) :60.32  O (ms) :16.579  P (ms) :0.106  Q (ms) :0.607  R (ms) :15.84  S (ms) :0.026

[링크 : http://www.epanorama.net/documents/pc/vga_timing.html]

+

640x480x60 에 빨간화면 확인

vga640x480 vga( CLOCK_50, KEY[0], LED, GP0[6], GP0[5], {GP0[16],GP0[19],GP0[18],GP0[21]}, {GP0[12],GP0[15],GP0[14],GP0[17]}, {GP0[8],GP0[9],GP0[10],GP0[13]} );

모니터에 따라 인식이 느리거나 안되기도 하네..

848x640x60 으로 인식... 머야(요즘 24인치 FHD LCD 모니터)

module vga640x480( input clk, input rst, output [7:0] LED, output reg hsync, output reg vsync, output [3:0] r, output [3:0] g, output [3:0] b ); reg clk25; reg [9:0] horizontal_counter; reg [9:0] vertical_counter; reg [9:0] X; reg [9:0] Y; wire [7:0] red; wire [7:0] green; wire [7:0] blue; assign r[3:0] = ((horizontal_counter >= 144)  && (horizontal_counter < 784)  && (vertical_counter >=39) && (vertical_counter < 519)) ? 4'b1111 : 4'b000;  assign g[1:0] = ((horizontal_counter >= 144)  && (horizontal_counter < 784)  && (vertical_counter >=39) && (vertical_counter < 519)) ? 4'b1111 : 4'b000;  assign b[2:0] = ((horizontal_counter >= 144)  && (horizontal_counter < 784)  && (vertical_counter >=39) && (vertical_counter < 519)) ? 4'b1111 : 4'b000;  assign red =   ((horizontal_counter >= 144)&&(horizontal_counter < 344) ) ? 4'b1111 : 4'b0000; assign green = ((horizontal_counter >= 344)&&(horizontal_counter < 544) ) ? 4'b1111 : 4'b0000; assign blue =  ((horizontal_counter >= 544)&&(horizontal_counter < 784) ) ? 4'b1111 : 4'b0000; always @(posedge clk) begin if (clk25 == 0) begin    clk25 <= 1; end    else begin clk25 <= 0;    end end always @(posedge clk25) begin if ((horizontal_counter > 0) && (horizontal_counter < 97))// -- 96+1 begin hsync <= 0; end else begin hsync <= 1; end  if ((vertical_counter > 0 ) && (vertical_counter < 3 )) //-- 2+1 begin vsync <= 0; end else begin vsync <= 1; end horizontal_counter <= horizontal_counter+1;      if (horizontal_counter == 800)  begin vertical_counter <= vertical_counter+1; horizontal_counter <= 0; end      if (vertical_counter == 521) begin vertical_counter <= 0; end end endmodule

[링크 : https://github.com/pmezydlo/DE0-Nano-SOC-VGA/blob/master/vgaram.v]