embeded/FPGA2017.12.06 15:33

아키텍쳐가 다른 것에 대한 비교는 무의미 하지만

그래도 굳이 하자면..

xilinx는 6 input 이고 altera는 4 input 이라

1.3배 정도 쳐주면 된다 라는 결론?


adaptive logic module (ALM)

logic elements (LEs)

[링크 : https://www.altera.com/en_US/pdfs/literature/wp/wp-01003.pdf]

LUT, Logic Cell and Logic Element are all the same to me: the most basic FPGA general logic primitive. Xilinx use LUT, Altera LE, microsemi/lattice possibly something else.

The problem is, they are not the same. In their most recent architecture, Xilinx use 6-input LUT and altera 4-input LUT. They are aggregated in logic blocks which has other features like fast-carry chain, registers and distributed memory.

Converting to system gates is useful, but don't forget it's also a marketing war. A Xilinx FPGA should fit 1.5 times the logic of an Altera FPGA, since it's LUT have 6 instead of 4, right? Well, it largely depends on the design, if the design can't use 6-inputs much, the unused ones are wasted. Same with fast-carry logic, I don't know if they count that in equivalent gate number, but be advised that number is inflated.

System gates is a common measure of ASIC design complexity. The same design on two different foundries should have similar system gates number, as waste is not really an issue for ASIC.

If you're looking for an FPGA. I suggest you choose your vendor, port enough of your design to get an idea of how big a FPGA you need and choose a FPGA with an upgrade path (if you want to market). If it's for a single prototype, just use the biggest FPGA you can afford. 

[링크 : https://stackoverflow.com/.../relation-between-luts-logic-cell-logic-elements-system-gates]


[링크 : http://ee.sharif.edu/~asic/Docs/fpga-logic-cells_V4_V5.pdf]



Cyclone IV 에는 LEs(Logic Elements)가

Logic array blocks (LABs) contain groups of LEs. 

Each LAB consists of the following features: 

■ 16 LEs

[링크 : https://www.altera.com/en_US/pdfs/literature/hb/cyclone-iv/cyiv-51002.pdf]


Cyclone V 에는 ALM이 언급되는데 LEs는 PCIe 관련으로 몇개의 LE가 사용된다 정도의 언급만 있다.

High-performance FPGA fabric Enhanced 8-input ALM with four registers 


The PCIe endpoint support includes multifunction support for up to eight functions, as shown in the following figure. The integrated multifunction support reduces the FPGA logic requirements by up to 20,000 LEs for PCIe designs that require multiple peripherals. 

[링크 : https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/cyclone-v/cv_51001.pdf]


근데.. LEs와 ALM을 동시에 표기한게 보이네.. 도대체 ALM과 LE의 연관이 어떻게 되는거야..

[링크 : https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/cyclone-v/cv_51001.pdf]


위에꺼랑 연관지어서 보면.. 25000 LEs = 9434 ALM 이고

평균적으로(?) 2.6LEs = 1 ALM 이 되는 건가?


음.. 아무튼 ALE와 LEs의 연관은 모르겠으나.. 

결론은 성능과 비용 사이에서 적절한 LUT4를 택했다 인가?

Designing the ALM The ALM is radically different from any other FPGA logic block, offering a number of major innovations. Getting from a classic 4-LUT with a single register block (with associated carry logic) to the ALM required a detailed understanding of customer requirements and a large investment in researching the tradeoffs of various architectures. Our pursuit for a larger LUT was inspired by research results indicating that a basic 6-LUT could yield a 14% performance improvement by reducing the number of levels of logic elements on the critical paths of circuits. Unfortunately, this performance increase also had a large area penalty, a 17% area increase resulting from a larger LUT-mask and more inputs for the LUT. Figure 4 illustrates the tradeoff between cost and delay for different sizes of LUTs. The basic approach in designing the ALM was to investigate building a larger LUT to reduce levels of logic and increase performance, but to also avoid the area increase by efficiently dividing the larger LUT into smaller LUTs when appropriate, as illustrated by the dashed line. The ability to divide a LUT is what makes it “adaptive.”  

[링크 : https://www.altera.com/en_US/pdfs/literature/wp/wp-01003.pdf]

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