Programming/VHDL VERILOG2018.01.12 13:28

함수 만들듯 verilog module을 만들어서

KEY 누르면 LED에 AND OR 연산해서 보여주려고 했더니

이상한 오류들이 뿜뿜하는 바람에 찾아 봤더니

module로 해서 구조적(함수 콜하듯)으로 사용할 때에는 wire로 된 값을 넘겨 주어야 하는 듯?

[링크 : https://blog.naver.com/bungkun1349/220337637928]

[링크 : https://blog.naver.com/specialist0/220777659022]


There is no strict definition of these terms, according to the IEEE Std. However, customarily, structural refers to describing a design using module instances (especially for the lower-level building blocks such as AND gates and flip-flops), whereas behavioral refers to describing a design using always blocks.

Gate netlists are always structural, and RTL code is typically behavioral. It is common for RTL to have instances of clock gates and synchronizer cells. 

[링크 : https://stackoverflow.com/.../what-is-the-difference-between-structural-verilog-and-behavioural-verilog]


11. Structural vs. Behavioral Verilog

To clarify the difference between structural and behavioral verilog: 
Structural verilog is composed of module instances and their interconnections (by wires) only.  The use of regs, explicit time delays, arithmetic expressions, procedural assignments, or other verilog control flow structures are considered behavioral verilog.

As stated earlier, your project code will consist primarily of structural verilog.  You will use behavioral statements for debugging purposes only.  In fact, you will probably only instantiate two regs in your whole design: one for the clock and one for a RESET signal that is asserted at the beginning of your simulation.

This section has described all of the Verilog functionality you will need for your final project.   If you want more information on behavioral Verilog, try reading the Bucknell CSCI Verilog Manual or the verilog manual at The University of Edinburgh. 

[링크 : http://users.ece.utexas.edu/~patt/04s.382N/tutorial/verilog_manual.html#11. Behavioral Verilog]

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