nios II 단종

2023년 6월 9일 단종 공고가 떴었다.

그럼 quartus도 22.x 까지만 지원할 것 같은데. 아예 사라진건진 봐야 알 듯.

[링크 : https://www.reddit.com/r/FPGA/comments/1492bx0/intel_discontinues_nios_ii_ip/]

 

nios v/m nios v/g 로 대체라면 기존의 ii/e ii/f 중에 f가 바뀌나?

ipr-nios가 정식으로 쓰는거고 ip-nios는 evaluation 이라는데(1시간 이후 멈춤) 맞나?

[링크 : https://www.intel.com/content/www/us/en/content-details/781327/intel-is-discontinuing-ip-ordering-codes-listed-in-pdn2312-for-nios-ii-ip.html]

 

그나저나 DMIPS 드럽게 낮네 

[링크 : https://docs.altera.com/r/docs/683629/current/nios-ii-performance-benchmarks/nios-ii-performance-benchmarks]

 

STM32F102x8 cortex-m3의 경우 1.25DMIPS 라는데 시기가 차이 있다 하더라도 nios ii/f가 제법 처참하다 싶다.

1.25 DMIPS/MHz (Dhrystone 2.1)

[링크 : https://www.st.com/resource/en/datasheet/stm32f102c8.pdf]

 

17년 이후로 Nios ii gen 2로 바뀌면서 nios ii/s는 사라지고 f만 남은거 같은데

그러면 위에 ip-nios랑 ipr-nios는 f인가? 머지?

Nios II classic is offered in 3 different configurations: Nios II/f (fast), Nios II/s (standard), and Nios II/e (economy). Nios II gen2 is offered in 2 different configurations: Nios II/f (fast), and Nios II/e (economy). Nios II/f The Nios II/f core is designed for maximum performance at the expense of core size. Features of Nios II/f include: Separate instruction and data caches (512 B to 64 KB) Optional MMU or MPU Access to up to 2 GB of external address space Optional tightly coupled memory for instructions and data Six-stage pipeline to achieve maximum DMIPS/MHz Single-cycle hardware multiply and barrel shifter Optional hardware divide option Dynamic branch prediction Up to 256 custom instructions and unlimited hardware accelerators JTAG debug module Optional JTAG debug module enhancements, including hardware breakpoints, data triggers, and real-time trace Nios II/s Nios II/s core is designed to maintain a balance between performance and cost. This core implementation is not longer supported for Altera Quartus II v.17 and newer. Features of Nios II/s include: Instruction cache Up to 2 GB of external address space Optional tightly coupled memory for instructions Five-stage pipeline Static branch prediction Hardware multiply, divide, and shift options Up to 256 custom instructions JTAG debug module Optional JTAG debug module enhancements, including hardware breakpoints, data triggers, and real-time trace Nios II/e The Nios II/e core is designed for smallest possible logic utilization of FPGAs. This is especially efficient for low-cost Cyclone II FPGA applications. Features of Nios II/e include: Up to 2 GB of external address space JTAG debug module Complete systems in fewer than 700 LEs Optional debug enhancements Up to 256 custom instructions Free, no license required

[링크 : https://en.wikipedia.org/wiki/Nios_II]

 

+

ai 답변

quartus 19.1 부터 EDS 제거되면서 윈도우에서 WSL 필요

quartus 24.1 부터 nios ii / eds 제거

 

+

레딧도 그렇지만 정말 취미(?) 사용자를 위해서는 두 회사가 더 멀어지고 있지만

altera는 intel에 인수되면서 더 심화된것 같고. 그래서 altera가 다시 intel과 결별한게 아닌가 싶다.

[링크 : https://www.cio.com/article/3964395/인텔-알테라-지분-51-매각···-fpga-사업-정리해-구조-개.html]

 

이 추세면.. xilinx로 갈아타야 하려나.. 쩝..

terasic 형님들 de0-nano-soc 처럼 쌈박한 zynq 내주실 생각 없습니까!?!??!