embeded/FPGA - ALTERA2018.05.30 15:14

DE0-nano에 실습중

일단.. module 선언이 아래 있던 위에있던 상관이 없나 보네..

머가 잘못되서 안되었던건지 모르겠지만 아무튼 책 보고 따라 치니 작동은 한다.


//=======================================================

//  This code is generated by Terasic System Builder

//=======================================================

module PwmCtrl(RST_N, CLK, LED0);

input RST_N, CLK;

output LED0;

reg[27:0] counter0;

always @(negedge RST_N or posedge CLK)

begin

if(RST_N == 1'b0)

begin

counter0 <= 0;

end else begin

counter0 <= counter0 + 1;

end

end

assign LED0 = counter0[26];

endmodule


module DE0_NANO(

//////////// CLOCK //////////

CLOCK_50,

//////////// LED //////////

LED,

//////////// KEY //////////

KEY 

);


//=======================================================

//  PARAMETER declarations

//=======================================================



//=======================================================

//  PORT declarations

//=======================================================


//////////// CLOCK //////////

input           CLOCK_50;

//////////// LED //////////

output      [7:0] LED;

//////////// KEY //////////

input      [1:0] KEY;


//=======================================================

//  REG/WIRE declarations

//=======================================================


//=======================================================

//  Structural coding

//=======================================================

PwmCtrl pwm(KEY[0],

CLOCK_50,

LED[0]);

endmodule 


원래는 counter0[27] 인데 너무 느려서 counter0[26]으로 변경


그리고 signalTap 이용해서 데이터 받아봄

(PLL 사용해서 클럭 분주하고 그걸 이용해 샘플링 주기를 변경해 봐야 할 듯)

2018/05/30 - [embeded/FPGA - ALTERA] - signal Tap 2와 talkback?

2018/05/24 - [embeded/FPGA - ALTERA] - altera signalTap <<

Posted by 구차니

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