embeded/FPGA - XILINX2018.03.15 15:52

Implementing SMPTE SDI Interfaces with Artix-7 FPGA GTP Transceivers

[링크 : https://www.xilinx.com/support/documentation/application_notes/xapp1097-smpte-sdi-a7-gtp.pdf]


순서도 약자도 모르겠다.

일단 대충 정리하면 아래정도 순서가 되려나?

GTP(3.2~6.6Gbps)

GTR(6.0Gbps)

GTX(12.5Gbps)

GTH(16.3Gbps)

GTZ(28.05Gbps)

GTY(32.75Gbps)

GTM(58.0Gbps)


7 Series and 6 Series(Spartan)

GTP(3.2~6.6Gbps) Power optimized

GTX(12.5Gbps) low jitter and strongest qualization 이니 Xtrong(던킨 커피냐!) 인가?

GTH(16.3Gbps) High performance

GTZ(28.05Gbps) Jitter니까 Z?


UltraScale

GTR(6.0Gbps) integRated? pRotocol?

GTH(16.3Gbps) High performance

GTY(32.75Gbps) X 다음꺼라 Y?

GTM(58.0Gbps) Maximum performance


  • UltraScale+ GTR (6.0 Gb/s): Easiest integration of common protocols to the Zynq Processor Subsystem
  • UltraScale+ GTH (16.3 Gb/s): Low power & high performance for the toughest backplanes
  • UltraScale+ GTY (32.75 Gb/s): Maximum NRZ performance for the fastest optical and backplane applications; 33G transceivers for chip-to-chip, chip-to-optics, and 28G backplanes
  • UltraScale GTH (16.3 Gb/s): Low power & high performance for the toughest backplanes
  • UltraScale GTY (30.5 Gb/s): High performance for optical and backplane applications; 30G transceivers for chip-to-chip, chip-to-optics, and 28G backplanes
  • UltraScale+ GTM (58 Gb/s): Maximum performance using PAM4 for 58G chip-to-chip, chip-to-optics, and backplane applications
  • 7 Series GTP (6.6 Gb/s): Power optimized transceiver for consumer and legacy serial standards
  • 7 Series GTX (12.5 Gb/s): Lowest jitter and strongest equalization in a mid-range transceiver
  • 7 Series GTH (13.1 Gb/s): Backplane and optical performance through world class jitter and equalization
  • 7 Series GTZ (28.05 Gb/s): Highest rate, lowest jitter 28G transceiver in a 28nm FPGA
  • Spartan-6 GTP (3.2 Gb/s): Power and cost optimized transceiver for cost-sensitive applications


아무튼.. 웬지 조만간 쓸모없이 이런거 해볼지도...?!

[링크 : https://www.xilinx.com/products/technology/high-speed-serial.html]

  [링크 : https://www.xilinx.com/support/documentation/user_guides/ug482_7Series_GTP_Transceivers.pdf]

  [링크 : https://www.xilinx.com/support/documentation/user_guides/ug476_7Series_Transceivers.pdf]


공식적인 약어는 없다는데

[링크 : https://forums.xilinx.com/t5/Virtex-Family-FPGAs/What-does-GTP-GTX-stand-for/td-p/18238]


RocketIO를 흡수하면서 생겨난 기술이라. 

그걸 추적하면 무언가 있을거 같은데 찾기 귀찮음..

'embeded > FPGA - XILINX' 카테고리의 다른 글

vivado device constraint  (0) 2018.03.20
vivado language template  (0) 2018.03.20
xilinx 고속 시리얼 인터페이스  (0) 2018.03.15
xilinx zynq와 altera cyclone V 용어비교  (0) 2018.01.30
xilinx bitstram ecryption  (0) 2018.01.23
xilinx artix-7 프로젝트 빌드해봄  (0) 2018.01.07
Posted by 구차니

댓글을 달아 주세요